PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5
Freescale Semiconductor
21
Functional Blocks
6.6.2
Termination of Unused Signals
Termination is not needed on output signals. For bidirectional I/Os, tie signals high or low though a
resistor. Recommended resistor values are 2–10 K
Ω
. If the PCI arbiter is disabled by the power-on reset
configuration settings, these signals can be tied together to a common resistor. If the PCI interface is used
in 32-bit mode, PCI1_AD[63:32] should be left floating. No termination is needed.
For inputs, tie signals to their inactive state through a resistor. Recommended resistor values are 2–10 K
Ω
.
6.6.3
Specific Pin Usage
The PowerQUICC III does not implement for the PCI interface specific CLK and RST pins separately
from the rest of the device pins. Instead, the PCI CLK is realized on the SYSCLK input, and the PCI RST
is realized on the HRESET input.
6.7
Three Speed Ethernet Controller (TSEC)
The TSEC has one management interface that controls all external PHYs. The management interface of
TSEC1 controls the TBI PHY from TSEC1 as well as all external PHYs. The management interface of
TSEC2, shown in
, controls the TBI PHY from TSEC2 only.
Figure 6. TSEC Management Interface
6.7.1
Graceful Stop
The TSEC interfaces must be properly stopped by the graceful stop mechanism. Stopping the transmit and
receive buffers without using graceful stop can yield unpredictable results. The processor must first
gracefully stop the transmitter by setting the DMACTL[GTS] bit and confirming that it has completed by
polling the IEVENT [GTSC] bit. Only then should the transmitter be disabled by clearing the
MACCFG1[TxEN] bit.
GMII, TBI
GMII, TBI
MDC/MDIO
MDC/MDIO
TSEC 1
MAC
TSEC 1
TBI
PHY 1
TSEC 2
MAC
PHY 2
TSEC 2
TBI
