PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5
16
Freescale Semiconductor
Functional Blocks
The start value is 0xFFFFFFFF. The final XOR value is 0x00000000.
5.4
Boot Hold-off Mode
The PowerQUICC III can be put into slave mode in a system. An external master on the PCI bus must
configure the device. Boot hold-off mode, when enabled during power-on reset, allows any external master
on these buses to configure the PowerQUICC III slave device. To enable this mode during power-on reset,
use the LA27 pin. During this mode, the core is suspended from fetching boot code. To exit this mode, the
EEBPCR[CPU_EN] bit must be set.
6
Functional Blocks
The following sections discuss the recommendations and guidelines for designing with the various
functional blocks on PowerQUICC III.
6.1
Global Utilities
The PowerQUICC III provides a global utilities block which controls power management, I/O device
enabling, power-on reset configuration monitoring, and other debug functions. Refer to
The following subsections present information on the device disable register (DEVDISR) and
low-power modes.
6.1.1
Device Disable Register (DEVDISR)
After the PowerQUICC III comes out of reset, all functional blocks are enabled. However, if all interfaces
of the PowerQUICC III are not used, it would be more power efficient to disable these interfaces. The
device disable register (DEVDISR) contains disable bits for the PCI1, PCI2, LBC, SEC, L2, DDR, e500,
Time Base, CPM, DMA, TSEC1, TSEC2, I2C, and DUART interface. If desired, the core or an external
master can disable these blocks by setting these bits.
When a block is disabled with this register, all clocks are disabled to the block, thereby saving power.
However, a result of not having clocks to an interface is that the interface does not respond to any interrupts
or accesses. A programming error occurs when the user tries to access configuration or status registers of
a block while disabled.
These interfaces cannot be re-enabled without asserting HRESET, or the results are be undefined.
Disabling the e500 core through this register is equivalent to “nap mode.” This is not recommended since
any interface disabled through DEVDISR requires an HRESET to re-enable it. Use the low-power “nap
mode” instead.
6.1.2
Low Power Modes
In addition to the device disable register, the PowerQUICC III further allows the user to reduce the power
consumption through the low-power modes. There are three low-power modes: doze, nap, and sleep. For
details on these modes, consult the relevant device manual. Putting the device into nap mode is equivalent
to disabling the e500 core through DEVDISR. However, because you cannot wake up the device using
DEVDISR, except through an HRESET, it is recommended that nap mode be used instead.
