PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5
6
Freescale Semiconductor
Clocking
2.6
PLL Power Supply Filtering
Each PowerQUICC III PLL is provided with power through independent power supply pins for the
MPC8555E, and MPC8541E (AV
DD
1, AV
DD
2, AV
DD
3, AV
DD
4, and AV
DD
5). The AV
DD
level should
always be equivalent to V
DD
, and preferably these voltages are derived directly from V
DD
through a
low-frequency filter as shown in
Figure 1. PLL Power Supply Filter Circuit
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is three
independent filter circuits, one to each of the three AV
DD
pins. Providing independent filters to each PLL
reduces the opportunity to cause noise injection from one PLL to the other. This circuit is intended to filter
noise in the PLL resonant frequency range, from 500 kHz to 10 MHz. It should be built with surface mount
capacitors with minimum effective series inductance (ESL). Each circuit should be placed as closely as
possible to the specific AV
DD
pin supplied to minimize noise coupled from nearby circuits. It should be
possible to route directly from the capacitors to the AV
DD
pin, which is on the periphery of the 783
FC-PBGA footprint, without the inductance of vias. If possible, a separate plane for each PLL filtering
circuit is recommended.
3
Clocking
3.1
System Clock
The system clock SYSCLK input is the primary clock source for all Synchronous blocks on the
PowerQUICC III and must always be provided. The SYSCLK input is multiplied by a phase-lock loop
(PLL) to generate the core complex bus (CCB) clock. The CCB clock is used by the L2 cache, CPM and
DMA. It is divided by two to generate the DDR clocks MCK[0:5]. It is divided by 2/4/8 (in the
LCRR[CLKDIV] register) to generate local bus clocks LCLK[0:2]. It is also multiplied by a second PLL
(by the power-on reset setting LALE, LGPL2) to generate the e500 core clock. As there are no default
settings for the two PowerQUICC III PLLs, power-on reset configuration of them within the system design
is mandatory.
The PCI interface has two clock modes, Synchronous mode, and Asynchronous mode. The default clock
mode (Synchronous) uses the SYSCLK. In Asynchronous mode each PCI (PCI1, PCI2) interface can be
configured to use separate PCI clock input unrelated to the SYSCLK input. The PCI clock modes are
configured during POR by TSEC2_TXD1, and TSEC2_TXD0 signals. See
V
DD
AV
DD
10
Ω
2.2 µF
2.2 µF
GND
Low ESL surface mount capacitors
