PowerQUICC III MPC8555E and MPC8541E Bring-Up Guidelines, Rev. 5
Freescale Semiconductor
19
Functional Blocks
Figure 5. Local Bus Connection to SDRAM
6.5.1
Termination of Signals During Normal Operation
You should verify signal integrity by simulating with the current IBIS model. A weak pull-up (2–10 K
Ω
)
is required on /LGTA signal.
6.5.2
Termination of Unused Signals
Termination is not needed on output signals. For bidirectional I/Os, tie signals high or low though a
resistor. Recommended resistor values are 2–10 K
Ω
. For inputs, tie signals to their inactive state through
a resistor. Recommended resistor values are 2–10 K
Ω
.
6.5.3
Timing
Local bus output valid, hold, and tri-state timings can be adjusted at reset by the POR pins
TSEC2_TXD[6:5]. These pins directly affect local bus AC-timing by adding up to three buffer delays to
the output path. The default configuration is a single buffer delay. Fewer buffer delays are needed in cases
where the connection is to a faster external device.
LSDA10
LSDDQM[0:3]
LCS1
LAD[0:31]
SDRAM
Local Bus
L
a
tc
h
Memory Address
LALE
LSDWE
32-Bit Port Size
LSDRAS
LSDCAS
Controller
LCKE
LCLK
LA[27:29]
WE
RAS
CAS
CS
DQM[3:0]
A10
A[11,9:3]
DQ[31:0]
CLK
CKE
A[2:0]
LAD[18,20:26]
Memory Data
LSDA10
LSDDQM[0:3]
LCS1
LAD[0:31]
SDRAM
Local Bus
L
a
tc
h
Memory Address
LALE
LSDWE
32-Bit Port Size
LSDRAS
LSDCAS
Controller
LCKE
LCLK
LA[27:29]
WE
RAS
CAS
CS
DQM[3:0]
A10
A[11,9:3]
DQ[31:0]
CLK
CKE
A[2:0]
LAD[18,20:26]
Memory Data
