Freescale Semiconductor FlexRay MFR4310, Reference Manual

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FlexRay Module (FLEXRAYV4)
MFR4310 Reference Manual, Rev. 2
Freescale Semiconductor 61
Figure 3-1. FlexRay Module Block Diagram
The protocol engine has two transmitter units TxA and TxB and two receiver units RxA and RxB for
sending and receiving frames through the two FlexRay channels. The time control unit (TCU) is
responsible for maintaining global clock synchronization to the FlexRay network. The overall activity of
the PE is controlled by the sequencer engine (SEQ).
The controller host interface provides host access to the module’s configuration, control, and status
registers, as well as to the message buffer configuration, control, and status registers. The message buffers
themselves, which contain the frame header and payload data received or to be transmitted, and the slot
status information, are stored in the FlexRay Memory (FRM).
The clock domain crossing unit implements signal crossing from the CHI clock domain to the PE clock
domain and vice versa, to allow for asynchronous PE and CHI clock domains.
The FlexRay module stores the frame header and payload data of frames received or of frames to be
transmitted in the FRM. The application accesses the FRM to retrieve and provide the frames to be
processed by the FlexRay module. In addition to the frame header and payload data, the FlexRay module
stores the synchronization frame related tables in the FRM for application processing.
NOTE
The FlexRay module does not provide a memory protection scheme for the
FlexRay Memory.
3.1.5 Features
The FlexRay module provides the following features:
Clock Domain Cross
ing
PE
TxA
RxA
TCU
config
SEQ
CHI
HIF
SEARCH
LUT
BCU
RXD_BG1
RXD_BG2
DBG0
TXD_BG1
TXEN1#
TXD_BG2
TXEN2#
DBG1
DBG2
DBG3
FlexRay Module
EBI
FlexRay
Memory
MIF