Freescale Semiconductor FlexRay MFR4310, Reference Manual

Page: 180 / 268

FlexRay Module (FLEXRAYV4)
MFR4310 Reference Manual, Rev. 2
180 Freescale Semiconductor
3.4.9.2 Receive FIFO Configuration
The receive FIFO control and configuration data are given in Section 3.4.3.7, “Receive FIFO Control and
Configuration Data”. The configuration of the receive FIFOs consists of two steps.
The first step is the allocation of the required amount of FRM for the FlexRay window. This includes the
allocation of the message buffer header area and the allocation of the message buffer data fields. For more
details see
Section 3.4.4, “FlexRay Memory Layout”.
The second step is the programming of the configuration data register while the PE is in POC:config.
The following steps configure the layout of the FIFO.
• The number of the first message buffer header index that belongs to the FIFO is written into the
Receive FIFO Start Index Register (RFSIR) .
• The depth of the FIFO is written into the FIFO_DEPTH field in the Receive FIFO Depth and Size
Register (RFDSR) .
• The length of the message buffer data field for the FIFO is written into the ENTRY_SIZE field in
the
Receive FIFO Depth and Size Register (RFDSR) .
NOTE
To ensure, that the read index RDIDX always points to a message buffer that
contains valid data, the receive FIFO must have at least 2 entries.
The FIFO filters are configured through the fifo filter registers.
3.4.9.3 Receive FIFO Reception
The frame reception to the receive FIFO is enabled, if for a certain slots no message buffer is assigned or
subscribed. In this case the FIFO filter path shown in
Figure 3-128 is activated.
When the receive FIFO filter path indicates that the received frame must be appended to the FIFO, the
FlexRay module writes the received frame header and slot status into the message buffer header field
indicated by the internal FIFO header write index. The payload data are written in the message buffer data
field. If the status of the received frame indicates a valid frame, the internal FIFO header write index is
updated and the fifo not-empty interrupt flag FNEAIF/FNEBIF in the
Global Interrupt Flag and Enable
Register (GIFER) is set.
3.4.9.4 Receive FIFO Message Access
If the fifo not-empty interrupt flag FNEAIF/FNEBIF in the Global Interrupt Flag and Enable Register
(GIFER) is set, the receive FIFO contains valid received messages, which can be accessed by the
application.
The receive FIFO does not require locking to access the message buffers. To access the message the
application first reads the receive FIFO read index RDIDX from the
Receive FIFO A Read Index Register
(RFARIR) or Receive FIFO B Read Index Register (RFBRIR) , respectively. This index points to the
message buffer header field of the next message buffer that contains valid data. The application can access
the message data as described in
Section 3.4.3.3, “Receive FIFO”. When the application has read all
message buffer data and status information, it writes 1 to the fifo not-empty interrupt flags FNEAIF or