Fluke 863, Service Manual

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867B,863
Service Manual
2-20
The sum amplifier in U30 adds the reconstructed AC + DC input and the midpoint bias
signal from the second divider.
When the GMM is displaying waveforms, R145 and C99 form a filter that is selected by
the analog switch (U14-3, U14-4, U14-5, and U14-9.) The output of this filter is
connected to the input of the Fast A/D Converter.
The DC signal to be recombined with the AC signal can be found on TP29. Without any
DC input or with the selector in AC and the GMM input shorted, TP29 should read
approximately 1V (the center value of the Fast A/D Converter with zero input.)
Note
Test the operation of the comp amplifier by selecting the 300 mV dc range,
applying 300 mV dc to the input, and checking TP29 for 1.3V dc
The reconstructed input signal (to be digitized by the Fast A/D Converter) can be
observed on TP19. With either the selector in AC or in DC (with the GMM input
shorted), the AC portion of the signal has a 1V bias.
Note
When you use an oscilloscope to view the input of the Fast A/D Converter
(U10), use a probe with a short (2 inch) ground lead. View the signal
between U10-16 (VIN) and U10-20 (GND).
Waveform Triggering 2-37.
Overview 2-38.
The GMM uses software and hardware triggers to control waveform display and
frequency counter operation. A software trigger occurs automatically if no hardware
trigger has occurred for a fixed period.
The following types of hardware triggers are available:
•
Dual Trigger is the default, providing two adjustable thresholds. Dual triggering
thereby allows for adjustment of the hysteresis window.
•
Single Trigger can also be selected via the GMM Set Up function. Single trigger
incorporates a single adjustable threshold with fixed hysteresis.
•
External Trigger allows for an external single trigger input at the center GMM input
terminal.
•
Fixed-threshold trigger applies predetermined Dual Trigger threshold voltages when
the GMM is set for Glitch Capture.
•
Component Test uses an internally generated digital trigger.
Dual Trigger 2-39.
The trigger is enabled when the digital ASIC (U24) unasserts the trigger holdoff signal
on U24-75. The digital ASIC can then recognize a trigger asserted by the analog ASIC
on U30-53. The internal trigger signal is derived from the input measurable at TP19,
passes through a filter (R1 and C109), and is routed through U30-56 to two comparators
in the U30 analog ASIC.
The threshold levels are established by the following two pulse-width modulated digital-
to-analog converters (DACs) in the digital ASIC: