
PA-2007 Mainboard Manual
14
CPU Pipeline
When enabled, allows the CPU to execute the pipeline function.
The options are: Enabled (Default), Disabled.
DRAM Timing Control
Allows you to speed up the data access of VT82C586A.
The options are: Normal, Fast (Default), Turbo.
Enhanced Page Mode
When enabled, it allows the system BIOS to pre-determine the next access is
on or off page. This leads the start of precharge time if off page.
The options are: Enabled (Default), Disabled.
SDRAM Cycle Length
This feature appears only when SDRAM DIMMs are installed (BIOS auto
dection). If the CAS latency of your SDRAM DIMMs is 2, set at 2 to
enhance the system performance. If the CAS latency of your SDRAM
DIMMs is 3, stay with the default setting, 3.
The options are: 2, 3 (Default).
SDRAM Bank Interleave
This feature appears only when SDRAM DIMMs are installed (BIOS auto
dection). When the bank interleave function of the SDRAMs is enabled, the
data transacting performance is better than when it is disabled.
The options are: Enabled (Default), Disabled.
Linear Burst Mode
When enabled, allows you to configure the CPU to SRAM data read/wirte
mode. If you use a Cyrix CPU, select Enabled; if you use an Intel CPU or
AMD-K5 CPU, please stay with the default value, Disabled. Please refer to
page 14, SRAM.
OnChip IDE First Channel
When enabled, allows the IDE drive to use the first channel of the primary
IDE.
The options are: Enabled (Default), Disabled.
OnChip IDE Second Channel
When enabled, allows the IDE drive to use the second channel of the primary
IDE.
The options are: Enabled (Default), Disabled.
IDE Prefetch Mode