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FIBOCOM FM150-NA User Manual
Page 30 of 72
Pin Pin Name
I/O Reset Value Pin Description
Type
45 GND
-
-
GND
Power Supply
46 UIM2_RESET
O L
CMOS 3V/1.8V
CMOS
3V/1.8V
47 PERn0
I
-
PCIe RX Differential Signals
Negative
-
48 UIM2_PWR
PO -
SIM2 power supply, 3V/1.8V
CMOS
3V/1.8V
49 PERp0
I
-
PCIe RX Differential Signals Positive
-
50 PERST#
I
PD
Asserted to reset module PCIe
interface default. Active low, internal
pull up(10KΩ).
CMOS
3.3V/1.8V
51 GND
-
-
GND
Power Supply
52 CLKREQ#
O T
Asserted by device to request a PCIe
reference clock be available (active
clock state) in order to transmit data. It
also used by L1 PM Sub states
mechanism, asserted by either host or
device to initiate an L1 exit.
Active low, open drain output and
should add external pull up on platform.
CMOS
3.3V/1.8V
53 REFCLKN
I
-
PCIe Reference Clock signal
Negative
-
54 PEWAKE#
O T
Asserted to wake up system and
reactivate PCIe link from L2 to L0, it
depends on system whether supports
wake up functionality.
Active low, open drain output and
should add external pull up on platform.
CMOS
3.3V/1.8V
55 REFCLKP
I
-
PCIe Reference Clock signal
Positive
-
56 RFFE_SCLK
O PD
MIPI Interface Tunable ANT,
RFFE clock
CMOS 1.8V
57 GND
-
-
GND
Power Supply
58 RFFE_SDATA
I/O PD
MIPI Interface Tunable ANT,
RFFE data
CMOS 1.8V
