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FIBOCOM FM150-NA User Manual
Page 46 of 72
Pin# Pin Name
I/O Reset Value Description
Type
also used by L1 PM Sub states mechanism,
asserted by either host or device to initiate an
L1 exit.
Active low, internal pull up (10KΩ).
54
PEWAKE#
O
L
Wake up system and reactivate PCIe link from
L2 to L0, it depends on system whether
supports wake up functionality.
Active low, open drain output and should add
external pull up on platform.
1.8V/3.3V
3.4.1.2 PCIe Interface Application
The reference circuit is shown in Figure 3-12:
Module side
AP side
AC Caps
AC Caps
PERST#
CLKREQ#
WAKE#
PERST#(pin50)
CLKREQ#(pin52)
PEWAKE#(pin54)
PERn0
PERP0
PETn0
PETP0
REFCLKN
REFCLKP
PETn0(pin41)
PETP0(pin43)
PERn0(pin47)
PERP0(pin49)
REFCLKN(pin53)
REFCLKP(pin55)
+3.3V/1.8V
10K
10K
M
.2
K
ey
-B
75
pi
n
C
on
ne
ct
or
Figure 3-12 Reference Circuit for PCIe Interface
FM150 module supports PCIe Gen3 interface, including three difference pairs: transmit pair TXP/N,
receiving pair RXP/N and clock pair CLKP/N.
PCIe can achieve the maximum transmission rate of 8 GT/s, and must strictly follow the rules below in
PCB Layout:
The differential signal pair lines shall be parallel and equal in length;
The differential signal pair lines shall be short if possible and be controlled within 15 inch(380 mm) for
AP end;
The impedance of differential signal pair lines is recommended to be 100 ohm, and can be controlled
to 80
～
120 ohm in accordance with PCIe protocol;
