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FIBOCOM FM150-NA User Manual
Page 42 of 72
+3.8V
PERST#
RESET#
Module State
Initialization
Activation
FCPO#
typical 30s
Activation
t
off
Finalization
OFF
AT+CFUN=0
t
off2
t
off1
t
on1
t
on2
t
sd
Figure 3-9 Reset timing2
nd
Index Min.
Recommended Max.
Comments
t
off1
16ms 20ms
-
RESET# should be asserted after PERST#,
refer
section 3.3.2
t
off2
0
-
-
FCPO# should be asserted after RESET#,
refer
section 3.3.2
t
off
500ms 2s
-
Time to allow the WWAN module to fully discharge any
residual voltages before the pin could be de-asserted
again. This is required for both Pre-OS as well as Runtime
flow.
t
on1
0
-
-
RESET# should be de-asserted after FCPO#,
refer
section 3.3.1.2
t
on2
50ms
100ms
-
The time delay of PERST# de-asserted after FCPO#,
PERST# must always be the last to get de-asserted.
refer
section 3.3.1.2
Notes:
1. RESET# is a sensitive signal, it’s recommended to add a filter capacitor close to the module.
In case of PCB layout, the RESET# signal lines should keep away from the RF interference
and protected by GND. Also, the RESET# signal lines shall neither near the PCB edge nor
route on the surface planes to avoid module from reset caused by ESD problems.
2. If the PCIe and USB interfaces connected to the host, and USB is used as the data
transmission interface, PERST# please do not follow the timing.
