M
ODEL
SL900A V
ERSION
V_1.0
P
REPARED BY
H/W
D
ATE
2006.06.30
S
UBJECT
T
ECHNICAL
M
ANUAL
P
AGE
17/51
SL900A
T
ECHNICAL
M
ANUAL
3.4
Direct Memory Access
A generic DMA controller is placed on Layer2 AHB Bus to support fast data transfer snd to off-load the
processor. With this controller, specific devices on AHB or APB buses can benefit greatly from quick
completion of data movement from or to memory modules such as Internal System Ram or External SRam.
Such generic DMA Controller can also be used to connect any two devices other than memory module as
long as they can be addressed in memory space.
Figure 9. Variety data paths of DMA transfer.
3.5
Interrupt Controller
Figure 10 outlines the major functionality of the MCU Interrupt Controller. The interrupt controller
processes all interrupt sources coming from external lines and internal MCU peripherals. Since ARM7EJ-S
core supports two levels of interrupt latency. This controller generates two request signals : FIQ for fast,
low latency interrupt request and IRQ for more general interrupts with lower priority.
Figure 10. Block Diagram of Interrupt controller.
Summary of Contents for SL900A
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