M
ODEL
SL900A V
ERSION
V_1.0
P
REPARED BY
H/W
D
ATE
2006.06.30
S
UBJECT
T
ECHNICAL
M
ANUAL
P
AGE
14/51
SL900A
T
ECHNICAL
M
ANUAL
3.1
Processor Core
The Micro-Controller Unit subsystem in MT6226M uses the 32-bit Arm7EJ-S RISC processor that is
based on the Von Neumann architecture with a single 32-bit data bus carrying both instructions and data.
The memory interface of ARM7EJ-S is totally compliant to AMBA based bus system, which allows direct
connection to the AHB Bus.
3.2
Memory Management
The processor core of MT6226M supports only memory addressing method for instruction fetch and data
access. It manages a 32bit address space that has addressing capability up to 4GB. System RAM, System
ROM , Registers, MCU Peripherals and external components are all mapped onto such 32-bit address space,
as depicted in Figure 7.
Figure 7. Memory Layout of MT6226M
External Memory Access
To allow external access, The MT6226M outputs 26bits(A25~A0) of address line along with 8 selection
signals that correspond to associated memory blocks. This is, MT6226M can support up to 8 MCU
addressable external components. The data width of internal system bus is fixed at 32bit wide, while the
data width of the external components can be either 8 or 16 bits.
Summary of Contents for SL900A
Page 1: ...SL900A SL900A ...
