M
ODEL
SL900A V
ERSION
V_1.0
P
REPARED BY
H/W
D
ATE
2006.06.30
S
UBJECT
T
ECHNICAL
M
ANUAL
P
AGE
36/51
SL900A
T
ECHNICAL
M
ANUAL
B2PSI
MT6226M use 3 wires B2PSI interface connected to PMIC, this bi-directional serial bus interface allows
baseband to write command to and read from PMIC. The bus protocol utilizes a 16bits proprietary format.
B2PSICK is the serial bus clock and is driven by the master. B2PSIDAT is the serial data; master or slave can
drive it. B2PSICS is the bus selection signal. Once the B2PSICS goes low, Baseband starts to transfer the 4
register bits followed by a read/write bit, then wait for 3 clocks for PMIC B2PSI state machine to decode the
Operation for the next succeeding 8 data bits. The State machine should count for 16 clocks to complete the data
transfer.
11.1
Clocks
There are two major time bases in the MT6226M. For the faster one is the 13MHz clock origination from an
off-chip temperature-compensated voltage controlled oscillator that can be 26MHz. This signal is the input from
the SYSCLK pad then is converted to the square-wave signal. The other time base is the 32.768KHz clock
generated by an on-chip oscillator connected to an external crystal.
Figure 37. Clock distributions in the MT6226M
- 32.768Khz Time Base
The 32.768Khz clock is always running. It’s mainly used as the time base of the Real Time
Clock(RTC) module, which maintains time and date with counters. In low power mode, the 13Mhz
time base is turned off, so the 32.768Khz clock shall be employed to update the critical TDMA timer
and Watchdog timer. This Time base is also used to clock the keypad Scanner logic. The C101,C102
must be tuned with Oscillator.
- 13Mhz Time Base
Two 1/2-dividers, one for MCU Clock and the other for DSP Clock, exist to allow usage of 26 or
13Mhz TXVCXO as clock input. There phase-locked loops(MPLL, DPLL and UPLL) are used to
generate three primary clocks.
MPLL : Provides the MCU System Clock.
Summary of Contents for SL900A
Page 1: ...SL900A SL900A ...
