CONFIDENTIAL
3
PCB Layout Design
3.3 Power Supply
Figure 15: ESP32S3 Power Traces in a Fourlayer PCB Design
• Four-layer PCB design is recommended over a two-layer design. The power traces should be routed on
Layer 4 (BOTTOM) whenever possible. Vias are required for the power traces to go through the layers and
get connected to the pins on the top layer. There should be at least two vias if the main power traces need
to cross layers. The drill diameter on other power traces should be no smaller than the width of the power
traces.
• The 3.3 V power traces, highlighted in yellow, are routed as shown in Figure
. The width of the main
power traces should be no less than 25 mil. The width of the power traces for VDD3P3 pins should be no
less than 20 mil. Recommended width of other power traces is 10 mil.
• The ESD protection diode is placed next to the power port (circled in red in the top left quarter of Figure
).
The power trace should have a 10 µF capacitor on its way to the chip, to be used in conjunction with a 0.1
µF capacitor. Then the power traces are divided into two ways from here and form a star-shape topology,
thus reducing the coupling between different power pins. Note that all decoupling capacitors should be
placed close to the power pin, and ground vias should be added close to the capacitor’s ground pin to
ensure a short return path.
• As shown in Figure
, it is recommended to connect the capacitor to ground in the LC filter circuit near
VDD3P3 pins to the fourth layer through a via, and maintain a keep-out area on other layers.
• The power trace begins at the power entrance and reaches VDD3P3. It is required to add GND isolation
between this power trace and the GPIO traces on the left, and place vias whenever possible.
• The ground pad at the bottom of the chip should be connected to the ground plane through at least nine
ground vias.
Espressif Systems
20
ESP32-S3 Series Hardware Design Guidelines v1.0
