CONFIDENTIAL
2
Schematic Checklist
Oscillator
If an oscillator is used, its output should be connected to XTAL_P on the chip through a series inductor (a 20 nH
inductor can be used initially). XTAL_N can be floating. Make sure that the oscillator output is stable and its
accuracy is within ±10 ppm. It is recommended that the circuit design for the oscillator is compatible with the
crystal. In case of defects in the circuit design, you can still use the crystal. The circuit for the oscillator is shown
in Figure
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
The values of C11, L2 and C12
vary with the actual PCB board.
The values of C1 and C4 vary with
the selection of the crystal.
The value of R4 varies with the actual
PCB board.
ESP32-S3R2
ESP32-S3
NC: No component.
ESP32-S3R8
SPICLK
SPICS0
SPIHD
SPID
SPIWP
SPIQ
SPICS0
LNA_IN
RF_ANT
GPIO39
GPIO41
GPIO42
U0RXD
GPIO46
GPIO45
U0TXD
SPICLK
GPIO48
SPID
SPIQ
SPIWP
SPIHD
G
P
IO
1
6
G
P
IO
1
5
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
CHIP_PU
GPIO38
GPIO37
GPIO36
GPIO35
GPIO47
GPIO40
GPIO33
GPIO34
XTAL_P
VDD_SPI
GND
GND
GND
VDD33
GND
GND
GND
GND
GND
VDD33
GND
GND
VDD33
GND
VDD33
GND
GND
GND
VDD_SPI
GND
GND
VDD33
GND
GND
GND
GND
VDD33
GND
GND
GND
C11
TBD
R16
0
C12
TBD
C13
0.1uF
C4
TBD
C15
0.1uF
R3
499
L3
TBD
R13
0
C14
1uF
U1
V
D
D
A
5
6
LNA_IN
1
VDD3P3
2
VDD3P3
3
GPIO0
5
GPIO1
6
GPIO2
7
GPIO3
8
GPIO4
9
GPIO5
10
GPIO6
11
GPIO7
12
G
P
IO
1
0
1
5
G
P
IO
1
1
1
6
G
P
IO
1
2
1
7
G
P
IO
1
3
1
8
G
P
IO
1
4
1
9
X
T
A
L
_
3
2
K
_
P
2
1
V
D
D
3
P
3
_
R
T
C
2
0
X
T
A
L
_
3
2
K
_
N
2
2
G
P
IO
1
7
2
3
G
P
IO
1
8
2
4
G
P
IO
1
9
2
5
G
P
IO
2
0
2
6
VDD_SPI
29
SPIWP
31
SPICS0
32
SPIQ
34
SPID
35
SPICLK
33
SPICLK_N
36
G
N
D
5
7
SPICLK_P
37
GPIO33
38
G
P
IO
3
8
4
3
G
P
IO
4
6
5
2
X
T
A
L
_
N
5
4
X
T
A
L
_
P
5
3
M
T
M
S
4
8
M
T
D
O
4
5
U
0
T
X
D
4
9
V
D
D
3
P
3
_
C
P
U
4
6
CHIP_PU
4
V
D
D
A
5
5
M
T
D
I
4
7
GPIO8
13
GPIO9
14
G
P
IO
2
1
2
7
S
P
IC
S
1
2
8
SPIHD
30
GPIO34
39
GPIO35
40
GPIO36
41
U
0
R
X
D
5
0
G
P
IO
4
5
5
1
GPIO37
42
M
T
C
K
4
4
C9
0.1uF
C3
1uF
R15
0
C6
10uF
L1
2.0nH
X
1
3
2
.7
6
8
k
H
z
1
2
R1
10K(NC)
U2
FLASH-3V3
V
D
D
8
G
N
D
4
/CS
1
CLK
6
/HOLD
7
/WP
3
DO
2
DI
5
C10
0.1uF
Y1
40MHz(±10ppm)
X
IN
1
G
N
D
2
X
O
U
T
3
G
N
D
4
R12
TBD
L2
TBD
C7
1uF
R4
0
C1
TBD
ANT1
PCB_ANT
1
2
C1
10nF
Y1
40MHz(±10ppm)
VDD
4
Tri-State
1
GND
2
OUT
3
R10
0
R
4
0
C
1
8
T
B
D
C2
10nF
C
1
7
T
B
D
R14
0
C8
0.1uF
Figure 7: Schematic for the Oscillator
Notice:
Defects in the manufacturing of crystal and oscillators (for example, large frequency deviation of more than ±10 ppm,
unstable performance within operating temperature range, etc) may lead to the malfunction of ESP32-S3, resulting in a
decrease of the RF performance.
2.4.2 RTC (optional)
ESP32-S3 supports an external 32.768 kHz crystal or an external signal (e.g., an oscillator) to act as the RTC
sleep clock. Figure
shows the schematic for the external 32.768 kHz crystal.
5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
T
h
e
v
a
lu
e
s
o
f C1
1
,
L
2
a
n
d
C1
2
v
a
ry
w
ith
th
e
a
ctu
a
l P
CB
b
o
a
rd
.
T
h
e
v
a
lu
e
s o
f C1
a
n
d
C4
v
a
ry
w
ith
th
e
se
le
ctio
n
o
f th
e
cr
y
sta
l.
T
h
e
v
a
lu
e
o
f R4
v
a
rie
s
w
ith
th
e
a
ctu
a
l
P
CB
b
o
a
rd
.
E
S
P
3
2
-S
3
R
2
E
S
P
3
2
-S
3
NC:
No
co
m
p
o
n
e
n
t.
E
S
P
3
2
-S
3
R
8
SPICLK
SPICS0
SPIHD
SPID
SPIWP
SPIQ
SPICS0
LNA_IN
RF_ANT
GPIO39
GPIO41
GPIO42
U0RXD
GPIO46
GPIO45
U0TXD
SPICLK
GPIO48
SPID
SPIQ
SPIWP
SPIHD
GPIO16
GPIO15
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
CHIP_PU
GPIO38
GPIO37
GPIO36
GPIO35
GPIO47
GPIO40
GPIO33
GPIO34
XTAL_P
VDD_SPI
GND
GND
GND
VDD33
GND
GND
GND
GND
GND
VDD33
GND
GND
VDD33
GND
VDD33
GND
GND
GND
VDD_SPI
GND
GND
VDD33
GND
GND
GND
GND
VDD33
GND
GND
GND
C11
TBD
R16
0
C12
TBD
C13
0.1uF
C4
TBD
C15
0.1uF
R3
499
L3
TBD
R13
0
C14
1uF
U1
VDDA
56
LNA_IN
1
VDD3P3
2
VDD3P3
3
GPIO0
5
GPIO1
6
GPIO2
7
GPIO3
8
GPIO4
9
GPIO5
10
GPIO6
11
GPIO7
12
GPIO10
15
GPIO11
16
GPIO12
17
GPIO13
18
GPIO14
19
XTAL_32K_P
21
VDD3P3_RTC
20
XTAL_32K_N
22
GPIO17
23
GPIO18
24
GPIO19
25
GPIO20
26
VDD_SPI
29
SPIWP
31
SPICS0
32
SPIQ
34
SPID
35
SPICLK
33
SPICLK_N
36
GND
57
SPICLK_P
37
GPIO33
38
GPIO38
43
GPIO46
52
XTAL_N
54
XTAL_P
53
MTMS
48
MTDO
45
U0TXD
49
VDD3P3_CPU
46
CHIP_PU
4
VDDA
55
MTDI
47
GPIO8
13
GPIO9
14
GPIO21
27
SPICS1
28
SPIHD
30
GPIO34
39
GPIO35
40
GPIO36
41
U0RXD
50
GPIO45
51
GPIO37
42
MTCK
44
C9
0.1uF
C3
1uF
R15
0
C6
10uF
L1
2.0nH
X1
32.768kHz
1
2
R1
10K(NC)
U2
FLASH-3V3
VDD
8
GND
4
/CS
1
CLK
6
/HOLD
7
/WP
3
DO
2
DI
5
C10
0.1uF
Y1
40MHz(±10ppm)
XIN
1
GND
2
XOUT
3
GND
4
R12
TBD
L2
TBD
C7
1uF
R4
0
C1
TBD
ANT1
PCB_ANT
1
2
C1
10nF
Y1
40MHz(±10ppm)
VDD
4
Tri-State
1
GND
2
OUT
3
R10
0
R4
0
C18
TBD
C2
10nF
C17
TBD
R14
0
C8
0.1uF
Figure 8: Schematic for the External Crystal (RTC)
Notice:
• Please note the requirements for the 32.768 kHz crystal.
–
Equivalent series resistance (ESR)
⩽
70
k
Ω
.
–
Load capacitance at both ends should be configured according to the crystal’s specification.
• The parallel resistor R is used for biasing the crystal circuit (5 M
Ω
< R
⩽
10
M
Ω
). In general, you do not need to
populate the resistor.
• If the RTC source is not required, then the pins for the external 32.768 kHz crystal can be used as other GPIOs.
Espressif Systems
12
ESP32-S3 Series Hardware Design Guidelines v1.0