Espressif ESP32--S3 Series Hardware Design Manuallines Download Page 5

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CONFIDENTIAL

Overview

1 Overview

Note:

Check the link or the QR code to make sure that you use the latest version of this document:

https://espressif.com/sites/default/files/documentation/esp32-s3_hardware_design_guidelines_en.

pdf

ESP32-S3 is a highly-integrated, low-power, 2.4 GHz Wi-Fi + Bluetooth

LE (5) System-on-Chip (SoC) solution.

It has the following features:

• Xtensa

32-bit LX7 CPU operating at clock speeds up to 240 MHz

• Complete Wi-Fi + Bluetooth subsystem integrating radio and baseband, RF switch, RF balun, power

amplifier, low noise amplifier (LNA), etc

• State-of-the-art power management unit

• Industry-leading RF performance

• Powerful AI computing ability

• Rich set of peripherals

ESP32-S3 also integrates advanced calibration circuitry that compensates for radio imperfections, and thus

reduces the cost and time to the market for your product, and eliminates the need for specialized testing

equipment.

The SoC is an ideal choice for a wide variety of application scenarios related to AI and Artificial Intelligence of

Things (AIoT), such as:

• Wake word detection

• Speech commands recognition

• Face detection and recognition

• Smart home

• Smart appliances

• Smart control panel

• Smart speaker

For more information about ESP32-S3 series, please refer to

ESP32-S3 Series Datasheet

Note:

Unless otherwise specified, ”ESP32-S3” used in this document refers to the series of chips, instead of a specific chip

variant.

Espressif Systems

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ESP32-S3 Series Hardware Design Guidelines v1.0

Summary of Contents for ESP32--S3 Series

Page 1: ...w to integrate ESP32 S3 into other products ESP32 S3 is a series of high performance Wi Fi and Bluetooth 5 LE SoCs These guidelines will help to ensure optimal performance of your product with respect to tech nical accuracy and conformity to Espressif s standards Version 1 0 Espressif Systems Copyright 2021 www espressif com ...

Page 2: ...of PCB Layout 17 3 2 Positioning a Module on a Base Board 18 3 3 Power Supply 20 3 4 Crystal Oscillator 21 3 5 RF 22 3 6 Flash and PSRAM 24 3 7 UART 24 3 8 USB 24 3 9 Touch Sensor 24 3 9 1 Electrode Pattern 25 3 9 2 PCB Layout 25 3 9 3 Waterproof and Proximity Sensing Design 26 3 10 Typical Layout Problems and Solutions 27 3 10 1 Q The current ripple is not large but the TX performance of RF is ra...

Page 3: ... Development 29 4 1 ESP32 S3 Modules 29 4 2 ESP32 S3 Development Boards 29 5 Related Documentation and Resources 30 Glossary 31 Revision History 32 Espressif Systems 3 Submit Documentation Feedback ESP32 S3 Series Hardware Design Guidelines v1 0 ...

Page 4: ...etup and Hold Times for the Strapping Pin 15 11 ESP32 S3 PCB Layout 17 12 Placement of ESP32 S3 Modules on Base Board antenna feed point on the right 18 13 Placement of ESP32 S3 Modules on Base Board antenna feed point on the left 18 14 Keepout Zone for ESP32 S3 Module s Antenna on the Base Board 19 15 ESP32 S3 Power Traces in a Four layer PCB Design 20 16 ESP32 S3 Analog Power Traces in a Four la...

Page 5: ...puting ability Rich set of peripherals ESP32 S3 also integrates advanced calibration circuitry that compensates for radio imperfections and thus reduces the cost and time to the market for your product and eliminates the need for specialized testing equipment The SoC is an ideal choice for a wide variety of application scenarios related to AI and Artificial Intelligence of Things AIoT such as Wake...

Page 6: ...2 S3 VDDA 56 LNA_IN 1 VDD3P3 2 VDD3P3 3 GPIO0 5 GPIO1 6 GPIO2 7 GPIO3 8 GPIO4 9 GPIO5 10 GPIO6 11 GPIO7 12 GPIO10 15 GPIO11 16 GPIO12 17 GPIO13 18 GPIO14 19 XTAL_32K_P 21 VDD3P3_RTC 20 XTAL_32K_N 22 GPIO17 23 GPIO18 24 GPIO19 25 GPIO20 26 VDD_SPI 29 SPIWP 31 SPICS0 32 SPIQ 34 SPID 35 SPICLK 33 SPICLK_N 36 GND 57 SPICLK_P 37 GPIO33 38 GPIO38 43 GPIO46 52 XTAL_N 53 XTAL_P 54 MTMS 48 MTDO 45 U0TXD 49...

Page 7: ...2 board and C4 vary with he crystal varies with the actual Optional SPICLK SPICS0 SPIHD SPID SPIWP SPIQ SPICS0 LNA_IN GPIO39 GPIO41 GPIO42 U0RXD GPIO46 GPIO45 U0TXD SPICLK GPIO48 SPID SPIQ SPIWP SPIHD GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 CHIP_PU GPIO38 GPIO37 GPIO36 GPIO35 GPIO47 GPIO40 GPIO33 GPIO34 GPIO10 GPIO11 GPIO12 GPIO12 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO2...

Page 8: ...lection of the crystal The value of R4 varies with the actual PCB board NC No component LNA_IN GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 CHIP_PU GPIO10 GPIO11 GPIO12 GPIO12 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 SPICS1 GPIO26 RF_ANT GND GND GND VDD33 GND GND GND GND GND VDD33 V GND GND GND VDD33 GND GND GND GND GND C11 TBD C12 TBD C4 TBD C15 0 1uF C5 TBD U1 ESP32...

Page 9: ...The reset voltage VIL_nRST should be in the range of 0 3 0 25 VDD V VDD is the I O voltage for a particular power domain of pins To avoid reboots caused by external interferences make the CHIP_PU trace as short as possible Also add a pull up resistor as well as a capacitor to the ground whenever possible Notice CHIP_PU pin must not be left floating 2 2 3 Power up and Reset Timing Figure 4 shows th...

Page 10: ...D ESP32 S3R2 SiP PSRAM 2 MB Quad SPI SPICLK CLK SPICS1 CE SPID SI SIO0 SPIQ SO SIO1 SPIWP SIO2 SPIHD SIO3 ESP32 S3R8 ESP32 S3R8V SiP PSRAM 8 MB Octal SPI SPICLK CLK SPICS1 CE SPID DQ0 SPIQ DQ1 SPIWP DQ2 SPIHD DQ3 GPIO33 DQ4 GPIO34 DQ5 GPIO35 DQ6 GPIO36 DQ7 GPIO37 DQS DM 2 3 2 External Flash and External RAM ESP32 S3 supports up to 1 GB external flash and 1 GB external RAM Make sure to select appro...

Page 11: ...apacitive values of C1 and C4 depend on further testing of and adjustment to the overall performance of the whole circuit In order to reduce the drive strength of the crystal and minimize the impact of crystal harmonics on RF performance a zero ohm series resistor on the XTAL_P clock trace is required Note that the accuracy of the selected crystal should be within 10 ppm 5 4 3 D C B The values of ...

Page 12: ...n external signal e g an oscillator to act as the RTC sleep clock Figure 8 shows the schematic for the external 32 768 kHz crystal 5 4 3 B A The values of C11 L2 and C12 vary with the actual PCB board ESP32 S3R2 ESP32 S3 NC No component ESP32 S3R8 SPICLK SPICS0 SPIHD SPICS0 LNA_IN RF_ANT SPICLK GPIO48 SPID SPIQ SPIWP SPIHD GPIO16 GPIO15 GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 C...

Page 13: ... GPIO1 6 GPIO2 7 GPIO3 8 GPIO4 9 GPIO5 10 GPIO6 11 GPIO7 12 GPIO10 15 GPIO11 16 GPIO12 17 GPIO13 18 GPIO14 19 XTAL_32K_P 21 VDD3P3_RTC 20 XTAL_32K_N 22 GPIO17 23 GPIO18 24 GPIO19 25 GPIO20 26 GND 57 GPIO46 52 XTAL_N 53 XTAL_P 54 MTMS 48 MTDO 45 U0TXD 49 VDD3P3_CPU 46 CHIP_PU 4 VDDA 55 MTDI 47 GPIO8 13 GPIO9 14 U0RXD 50 GPIO45 51 C9 TBD C3 1uF C6 10uF L1 0 L3 TBD R4 0 L2 TBD C7 1uF ANT1 PCB_ANT 1 2...

Page 14: ... the JTAG signal source Table 3 JTAG Signal Source Selection EFUSE_STRAP_JTAG_SEL EFUSE_DIS_USB_JTAG EFUSE_DIS_PAD_JTAG JTAG Signal Source 1 0 0 Refer to Table 4 0 0 0 USB Serial JTAG controller don t care 0 1 USB Serial JTAG controller don t care 1 0 On chip JTAG pins don t care 1 1 N A To change the strapping bit values users can apply the external pull down pull up resistances or use the host M...

Page 15: ...l during boot but if GPIO46 is 1 print is disabled 2 and GPIO46 is 0 print is disabled but if GPIO46 is 1 print is normal 3 print is disabled and not controlled by GPIO46 Figure 10 shows the setup and hold times for the strapping pin before and after the CHIP_PU signal goes high Details about the parameters are listed in Table 5 CHIP_PU tHD tSU Strapping pin VIL_nRST VIH Figure 10 Setup and Hold T...

Page 16: ...uce the coupling noise and interference on the line and to strengthen the ESD protection The recommended resistance is from 470 Ω to 2 kΩ preferably 510 Ω The specific value also depends on the actual test results of the product The ESP32 S3 touch sensor has a waterproof design and digital filtering function Note that only GPIO14 TOUCH14 can drive the shield electrode Espressif Systems 16 Submit D...

Page 17: ...ER GND plane should be applied to better isolate the RF and crystal oscillator parts It is acceptable to route signal traces on this layer provided that there is a complete GND plane under the RF and crystal oscillator Layer 4 BOTTOM Route power traces here It is not recommended to place any components on this layer A two layer PCB design can also be used Layer 1 TOP Signal traces and components L...

Page 18: ...rd PCB antenna should be placed outside the base board whenever possible In addition the feed point of the antenna should be closest to the board In the following example figures positions with mark are strongly recommended while positions without a mark are not recommended 1 2 3 4 5 Base board Feed Point Figure 12 Placement of ESP32 S3 Modules on Base Board antenna feed point on the right 1 2 3 4...

Page 19: ...its impact on the antenna Max 1 Base board Max 2 Min15 Unit mm Clearance Area 6 Figure 14 Keepout Zone for ESP32 S3 Module s Antenna on the Base Board If the product is designed with a layout that does not meet the above rules it is necessary to test the throughput and communication distance of the whole product to ensure product performance When designing an end product attention should be paid t...

Page 20: ...red in the top left quarter of Figure 15 The power trace should have a 10 µF capacitor on its way to the chip to be used in conjunction with a 0 1 µF capacitor Then the power traces are divided into two ways from here and form a star shape topology thus reducing the coupling between different power pins Note that all decoupling capacitors should be placed close to the power pin and ground vias sho...

Page 21: ... and output traces which means the traces cannot cross layers The external regulating capacitor should be placed on the near left or right side of the crystal oscillator and at the end of the clock trace whenever possible to make sure the ground pad of the capacitor is close to that of the crystal oscillator Do not route high frequency digital signal traces under the crystal oscillator It is best ...

Page 22: ...RF trace and placed close to the chip in a zigzag For designing the RF trace at 50 Ω single ended impedance please refer to the PCB stack up design shown in Figure 19 The RF trace should have consistent width and not branch out It should be as short as possible with dense ground vias around for inteference shielding The RF trace should be routed on the outer layer without vias i e should not cross...

Page 23: ...signal traces routed close to the RF trace The RF antenna should be placed away from high frequency components such as crystals DDR high frequency clocks etc In addition the USB port USB to serial chip UART signal lines including traces vias test points header pins etc must be as far away from the antenna as possible The UART signal line should be surrounded by ground copper and ground vias 0 33 4...

Page 24: ... vias 3 8 USB Place the RC circuit on the USB traces closer to the chip Please use differential pairs and route them in parallel at equal lengths Make sure there is a complete reference ground plane and surround the USB traces with ground copper 3 9 Touch Sensor ESP32 S3 offers up to 14 capacitive IOs that detect changes in capacitance on touch sensors due to finger contact or proximity The chip s...

Page 25: ...nd shape of an electrode improves system sensitivity Round oval or shapes similar to a human fingertip are commonly applied Large size or irregular shape might lead to incorrect responses from nearby electrodes Figure 23 Electrode Pattern Requirements Note The examples illustrated in Figure 23 are not of actual scale It is suggested to use a human fingertip as reference 3 9 2 PCB Layout Figure 24 ...

Page 26: ...ound the electrodes and traces The traces should be isolated well and routed away from that of the antenna 3 9 3 Waterproof and Proximity Sensing Design ESP32 S3 touch sensor has a waterproof design and features proximity sensor function Figure 25 shows an example layout of a waterproof and proximity sensing design Touch sensor TOUCH1 TOUCH14 Protective sensor TOUCH1 TOUCH14 Shied electrode 728 Fi...

Page 27: ...and Solutions 3 10 1 Q The current ripple is not large but the TX performance of RF is rather poor Analysis The current ripple has a strong impact on the RF TX performance It should be noted that the ripple must be tested when ESP32 S3 is in the normal working mode The ripple increases when the power gets high in a different mode Generally the peak to peak value of the ripple should be 80 mV when ...

Page 28: ...l way The EVM becomes poor as the signal distortion happens Solution Match the antenna s impedance with the π type circuit on the RF trace so that impedance of the antenna as seen from the RF pin matches closely with that of the chip This reduces reflections to the minimum 3 10 4 Q TX performance is not bad but the RX sensitivity is low Analysis Good TX performance indicates proper RF impedance ma...

Page 29: ...een downloaded in the flash If you need to download different firmware please follow the steps below 1 Set the module to UART Download mode by pulling IO0 pulled up by default and IO46 pulled down by default low 2 Power on the module and check whether the module has entered UART Download mode via serial port 3 Download your firmware into flash using Flash Download Tool 4 After firmware has been do...

Page 30: ...rticles and Notes from Espressif folks http blog espressif com See the tabs SDKs and Demos Apps Tools AT Firmware http espressif com en support download sdks demos Products ESP32 S3 Series SoCs Browse through all ESP32 S3 SoCs http espressif com en products socs id ESP32 S3 ESP32 S3 Series Modules Browse through all ESP32 S3 based modules http espressif com en products modules id ESP32 S3 ESP32 S3...

Page 31: ...tor PA Power Amplifier RC Resistor Capacitor RTC Real Time Clock RX Receive SiP System in Package TX Transmit Zero ohm resistor A zero ohm resistor is a placeholder on the circuit so that another higher ohm resistor can replace it depending on design cases Espressif Systems 31 Submit Documentation Feedback ESP32 S3 Series Hardware Design Guidelines v1 0 ...

Page 32: ...F I D E N T I A L Revision History Revision History Date Version Release Notes 2021 09 30 v1 0 First release Espressif Systems 32 Submit Documentation Feedback ESP32 S3 Series Hardware Design Guidelines v1 0 ...

Page 33: ...OUT OF ANY PROPOSAL SPECIFICATION OR SAMPLE All liability including liability for infringement of any proprietary rights relating to use of information in this document is disclaimed No licenses express or implied by estoppel or otherwise to any intellectual property rights are granted herein The Wi Fi Alliance Member logo is a trademark of the Wi Fi Alliance The Bluetooth logo is a registered tra...

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