Espressif ESP32--S3 Series, Hardware Design Manuallines

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CONFIDENTIAL
2 Schematic Checklist
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
The values of C11, L2 and C12
vary with the actual PCB board.
The values of C1 and C4 vary with
the selection of the crystal.
The value of R4 varies with the actual
PCB board.
NC: No component.
(Optional)
SPICLK
SPICS0
SPIHD
SPID
SPIWP
SPIQ
SPICS0
LNA_IN RF_ANT
GPIO39
GPIO41
GPIO42
U0RXD
GPIO46
GPIO45
U0TXD
SPICLK
GPIO48
SPID
SPIQ
SPIWP
SPIHD
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
CHIP_PU
GPIO38
GPIO37
GPIO36
GPIO35
GPIO47
GPIO40
GPIO33
GPIO34
G
P
IO
1
0
G
P
IO
1
1
G
P
IO
1
2
G
P
IO
1
2
G
P
IO
1
4
G
P
IO
1
5
G
P
IO
1
6
G
P
IO
1
7
G
P
IO
1
8
G
P
IO
1
9
G
P
IO
2
0
G
P
IO
2
1
S
P
IC
S
1
G
P
IO
2
6
SPICS1
SPICLK
SPIHD
SPID
SPIWP
SPIQ
VDD_SPI
GND GND GND
VDD33
GND GND GND
GND GND
VDD33
GND
GND
VDD33
GND
VDD33
GND
GND
GND
VDD_SPI
GND
GND
VDD33
GND
GND
GND
GND
VDD_SPI
R16 0
C11
TBD
C13
0.1uF
C12
TBD
C4
TBD
R3 499
C15
0.1uF
C14
1uF
R13 0
C3
1uF
C9
0.1uF
U1 ESP32-S3
V
D
D
A
5
6
LNA_IN
1
VDD3P3
2
VDD3P3
3
GPIO0
5
GPIO1
6
GPIO2
7
GPIO3
8
GPIO4
9
GPIO5
10
GPIO6
11
GPIO7
12
G
P
IO
1
0
1
5
G
P
IO
1
1
1
6
G
P
IO
1
2
1
7
G
P
IO
1
3
1
8
G
P
IO
1
4
1
9
X
T
A
L
_
3
2
K
_
P
2
1
V
D
D
3
P
3
_
R
T
C
2
0
X
T
A
L
_
3
2
K
_
N
2
2
G
P
IO
1
7
2
3
G
P
IO
1
8
2
4
G
P
IO
1
9
2
5
G
P
IO
2
0
2
6
VDD_SPI
29
SPIWP
31
SPICS0
32
SPIQ
34
SPID
35
SPICLK
33
SPICLK_N
36
G
N
D
5
7
SPICLK_P
37
GPIO33
38
G
P
IO
3
8
4
3
G
P
IO
4
6
5
2
X
T
A
L
_
N
5
4
X
T
A
L
_
P
5
3
M
T
M
S
4
8
M
T
D
O
4
5
U
0
T
X
D
4
9
V
D
D
3
P
3
_
C
P
U
4
6
CHIP_PU
4
V
D
D
A
5
5
M
T
D
I
4
7
GPIO8
13
GPIO9
14
G
P
IO
2
1
2
7
S
P
IC
S
1
2
8
SPIHD
30
GPIO34
39
GPIO35
40
GPIO36
41
U
0
R
X
D
5
0
G
P
IO
4
5
5
1
GPIO37
42
M
T
C
K
4
4
L1 2.0nH
C6
10uF
R15 0
Y1
40MHz(±10ppm)
X
IN
1
G
N
D
2
X
O
U
T
3
G
N
D
4
C10
0.1uF
U2 FLASH-3V3
V
D
D
8
G
N
D
4
/CS
1
CLK
6
/HOLD
7
/WP
3
DO
2
DI
5
R1
10K(NC)
U3 PSRAM-3V3
V
D
D
8
V
S
S
4
CS
1
SCLK
6
SIO3
7
SIO2
3
SO/SIO1
2
SI/SIO0
5
C7
1uF
L2 TBD
ANT1
PCB_ANT
1
2
C1
TBD
R10 0
R
4
0
C2
10nF
C8
0.1uF
R14 0
Figure 5: Schematic for the External Flash and RAM (PSRAM)
2.4 Clock Source
ESP32-S3 has two clock sources:
• External crystal oscillator clock source
• RTC clock source
2.4.1 External Clock Source (compulsory)
Currently, the ESP32-S3 firmware only supports 40 MHz crystal or oscillator.
Crystal
The circuit for the crystal is shown in Figure 6 . The specific capacitive values of C1 and C4 depend on further
testing of, and adjustment to, the overall performance of the whole circuit. In order to reduce the drive strength of
the crystal and minimize the impact of crystal harmonics on RF performance, a zero-ohm series resistor on the
XTAL_P clock trace is required. Note that the accuracy of the selected crystal should be within ±10 ppm.
5 5
4 4
3 3
2 2
1 1
D
D
C
C
B
B
A
A
T
h
e
v
a
lu
e
s
o
f C1
1
,
L
2
a
n
d
C1
2
v
a
ry
w
ith
th
e
a
ctu
a
l P
CB
b
o
a
rd
.
T
h
e
v
a
lu
e
s o
f C1
a
n
d
C4
v
a
ry
w
ith
th
e
se
le
ctio
n
o
f th
e
cr
y
sta
l.
T
h
e
v
a
lu
e
o
f R4
v
a
rie
s
w
ith
th
e
a
ctu
a
l
P
CB
b
o
a
rd
.
NC:
No
co
m
p
o
n
e
n
t.
(O
p
tio
n
a
l)
SPICLK SPICS0 SPIHD
SPID SPIWP SPIQ
SPICS0
LNA_IN
RF_ANT
GPIO39 GPIO41 GPIO42 U0RXD GPIO46 GPIO45 U0TXD SPICLK GPIO48 SPID SPIQ SPIWP SPIHD
GPIO9 GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 CHIP_PU
GPIO38 GPIO37 GPIO36 GPIO35 GPIO47 GPIO40 GPIO33 GPIO34
GPIO10
GPIO11
GPIO12
GPIO12
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
SPICS1 GPIO26
SPICS1 SPICLK SPIHD
SPID SPIWP SPIQ
VDD_SPI
GND
GND
GND
VDD33
GND
GND
GND
GND
VDD33
GND
GND
VDD33
GND
VDD33
GND
GND
GND
VDD_SPI
GND
GND
VDD33
GND
GND
VDD_SPI
GND
GND
GND
C11
TBD
R16
0
C12
TBD
C13 0.1uF
C4 TBD
C15
0.1uF
R3
499
R13
0
C14
1uF
U1
ESP32-S3
VDDA
56
LNA_IN
1
VDD3P3
2
VDD3P3
3
GPIO0
5
GPIO1
6
GPIO2
7
GPIO3
8
GPIO4
9
GPIO5
10
GPIO6
11
GPIO7
12
GPIO10
15
GPIO11
16
GPIO12
17
GPIO13
18
GPIO14
19
XTAL_32K_P
21
VDD3P3_RTC
20
XTAL_32K_N
22
GPIO17
23
GPIO18
24
GPIO19
25
GPIO20
26
VDD_SPI
29
SPIWP
31
SPICS0
32
SPIQ
34
SPID
35
SPICLK
33
SPICLK_N
36
GND
57
SPICLK_P
37
GPIO33
38
GPIO38
43
GPIO46
52
XTAL_N
53
XTAL_P
54
MTMS
48
MTDO
45
U0TXD
49
VDD3P3_CPU
46
CHIP_PU
4
VDDA
55
MTDI
47
GPIO8
13
GPIO9
14
GPIO21
27
SPICS1
28
SPIHD
30
GPIO34
39
GPIO35
40
GPIO36
41
U0RXD
50
GPIO45
51
GPIO37
42
MTCK
44
C9
TBD
C3
1uF
R15
0
C6
10uF
L1
0
R1
10K(NC)
U2
FLASH-3V3
VDD
8
GND
4
/CS
1
CLK
6
/HOLD
7
/WP
3
DO
2
DI
5
C10 0.1uF
Y1
40MHz(±10ppm)
XIN
1
GND
2
XOUT
3
GND
4
R4 0
L2
TBD
C7
1uF
U3
PSRAM-3V3
VDD
8
VSS
4
CS
1
SCLK
6
SIO3
7
SIO2
3
SO/SIO1
2
SI/SIO0
5
C1
TBD
ANT1 PCB_ANT
1 2
R10
0
C2
10nF
R14
0
C8 0.1uF
Figure 6: Schematic for the Crystal
Espressif Systems 11
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ESP32-S3 Series Hardware Design Guidelines v1.0