Espressif ESP32--S3 Series, Hardware Design Manuallines

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CONFIDENTIAL
2 Schematic Checklist
2.2 Power­on Sequence and System Reset
2.2.1 Power­on Sequence
ESP32-S3 uses a 3.3 V system power supply. The chip should be activated after the power rails have stabilized.
This is achieved by delaying the activation of CHIP_PU after the 3.3 V rails have been brought up. More details
can be found in Section 2.2.3 .
Notice:
To ensure that power is supplied to the chip during power-up, it is advised to add an RC delay circuit at the CHIP_PU
pin. The recommended setting for the RC delay circuit is usually R = 10 k Ω and C = 1 µ F. However, specific parameters
should be adjusted based on the power-up timing of the power supply and the power-up and reset sequence timing of
the chip.
2.2.2 System Reset
CHIP_PU serves as the reset pin of ESP32-S3. The reset voltage (V
IL _ nRST
) should be in the range of (–0.3 ~
0.25 × VDD) V. VDD is the I/O voltage for a particular power domain of pins. To avoid reboots caused by external
interferences, make the CHIP_PU trace as short as possible. Also, add a pull-up resistor as well as a capacitor to
the ground whenever possible.
Notice:
CHIP_PU pin must not be left floating.
2.2.3 Power­up and Reset Timing
Figure 4 shows the power-up and reset timing of ESP32-S3 series of SoCs. Details about the parameters are
listed in Table 1 .
VDDA,
VDD3P3,
VDD3P3_RTC,
VDD3P3_CPU
CHIP_PU
t0 t1
V
IL_nRST
2.8 V
Figure 4: ESP32­S3 Power­up and Reset Timing
Table 1: Description of ESP32­S3 Power­up and Reset Timing Parameters
Parameter Description Min (
µ
s)
t
0
Time between bringing up the power rails of VDDA, VDD3P3,
VDD3P3_RTC, VDD3P3_CPU and activating CHIP_PU
50
t
1
Duration of CHIP_PU signal level < V
IL _ nRST
to reset the chip 50
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ESP32-S3 Series Hardware Design Guidelines v1.0