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EPSON
S1C63666 TECHNICAL MANUAL
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
• When reading
When "1" is read: High level
When "0" is read: Low level
The serial data input from the SIN (P10) terminal can be read from these registers.
The serial data input from the SIN (P10) terminal is converted into parallel data, as a high (V
DD
) level bit
into "1" and as a low (V
SS
) level bit into "0", and is loaded to these registers. Perform data reading only
while the serial interface is not running (i.e., the synchronous clock is neither being input or output).
At initial reset, these registers are undefined.
EISIF: Interrupt mask register (FFE2H•D0)
Masking the interrupt of the serial interface can be selected with this register.
When "1" is written: Enabled
When "0" is written: Masked
Reading: Valid
With this register, it is possible to select whether the serial interface interrupt is to be masked or not.
At initial reset, this register is set to "0".
ISIF: Interrupt factor flag (FFF2H•D0)
This flag indicates the occurrence of serial interface interrupt.
When "1" is read: Interrupt has occurred
When "0" is read: Interrupt has not occurred
When "1" is written: Flag is reset
When "0" is written: Invalid
From the status of this flag, the software can decide whether the serial interface interrupt.
This flag is set to "1" after an 8-bit data input/output even if the interrupt is masked.
This flag is reset to "0" by writing "1" to it.
After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag = "1") is
set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure to reset
(write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the interrupt
enabled state.
At initial reset, this flag is set to "0".
4.12.6 Programming notes
(1) Perform data writing/reading to the data registers SD0–SD7 only while the serial interface is not
running (i.e., the synchronous clock is neither being input or output).
(2) As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be
performed prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated
through data writing/reading on data registers SD0–SD7.) In addition, be sure to enable the serial
interface with the ESIF register before setting the trigger.
Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from
performing trigger input multiple times, as leads to malfunctioning. Moreover, when the synchronous
clock SCLK is external clock, start to input the external clock after the trigger.
(3) Setting of the input/output permutation (MSB first/LSB first) with the SDP register should be done
before setting data to SD0–SD7.
(4) Be aware that the maximum clock frequency for the serial interface is limited to 1 MHz when OSC3 is
used as the clock source of the programmable timer or in the slave mode.
(5) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
