S1C63666 TECHNICAL MANUAL
EPSON
97
CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Serial Interface)
Pay attention to the polarity of the synchronous clock selected by the mask option because the selection
content is different.
The input data fetch timing may be selected but output timing for output data is fixed at the rising edge
_________
of SCLK (when positive polarity is selected) or at the falling edge of SCLK (when negative polarity is
selected).
At initial reset, this register is set to "0".
SDP: Data input/output permutation selection register (FF71H•D3)
Selects the serial data input/output permutation.
When "1" is written: MSB first
When "0" is written: LSB first
Reading: Valid
Select whether the data input/output permutation will be MSB first or LSB first.
At initial reset, this register is set to "0".
SCTRG: Clock trigger/status (FF70H•D1)
This is a trigger to start input/output of synchronous clock (SCLK).
• When writing
When "1" is written: Trigger
When "0" is written: No operation
When this trigger is supplied to the serial interface activating circuit, the synchronous clock (SCLK)
input/output is started.
As a trigger condition, it is required that data writing or reading on data registers SD0–SD7 be performed
prior to writing "1" to SCTRG. (The internal circuit of the serial interface is initiated through data writ-
ing/reading on data registers SD0–SD7.) In addition, be sure to enable the serial interface with the ESIF
register before setting the trigger.
Supply trigger only once every time the serial interface is placed in the RUN state. Refrain from perform-
ing trigger input multiple times, as leads to malfunctioning.
Moreover, when the synchronous clock SCLK is external clock, start to input the external clock after the
trigger.
• When reading
When "1" is read: RUN (during input/output the synchronous clock)
When "0" is read: STOP (the synchronous clock stops)
When this bit is read, it indicates the status of serial interface clock.
After "1" is written to SCTRG, this value is latched till serial interface clock stops (8 clock counts). There-
fore, if "1" is read, it indicates that the synchronous clock is in input/output operation.
When the synchronous clock input/output is completed, this latch is reset to "0".
At initial reset, this bit is set to "0".
SD0–SD3, SD4–SD7: Serial interface data register (FF72H, FF73H)
These registers are used for writing and reading serial data.
• When writing
When "1" is written: High level
When "0" is written: Low level
Write data to be output in these registers. The register data is converted into serial data and output from
the SOUT (P11) terminal; data bits set at "1" are output as high (V
DD
) level and data bits set at "0" are
output as low (V
SS
) level.
