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EPSON
S1C63666 TECHNICAL MANUAL
CHAPTER 5: SUMMARY OF NOTES
Sound generator
(1) Since it generates a buzzer signal that is out of synchronization with the BZE register, hazards may at
times be produced when the signal goes on/off due to the setting of the BZE register.
(2) The one-shot output is only valid when the normal buzzer output is off (BZE = "0") and will be invalid
when the normal buzzer output is on (BZE = "1").
Integer multiplier
An operation process takes 10 CPU clock cycles (5 bus cycles) after writing to the calculation mode
selection register CALMD until the operation result is set to the destination register DRH/DRL and
the operation flags. While this operation process, do not read/write from/to the destination register
DRH/DRL and do not read NF/VF/ZF.
R/f converter
(1) Depending on the initial value of the measurement counter (MC), the measurement counter or the
time base counter may overflow while the CR oscillation clock is being counted. When setting the
initial value, pay attention to CR oscillation frequency, its fluctuation range and the input clock
frequency of the time base counter. If an overflow occurs, R/f conversion is terminated immediately.
When the R/f conversion result (measurement counter value) is read, check the overflow flags
(OVMC and OVTBC). The upper limit of the CR oscillation frequency is 500 kHz. There is no lower-
limit but make sure that the time base counter does not overflow.
(2) When an interrupt occurs by the counter overflow, the same interrupt will occur if the overflow flag
(OVMC or OVTBC) is not reset. Be sure to check and reset to "0" (writing "1") the overflow flag when
the R/f converter interrupt occurs.
(3) When setting the measurement counter, always write 5 words of data continuously in order from the
lower address (FF92H
→
FF93H
→
FF94H
→
FF95H
→
FF96H). Furthermore, an LD instruction
should be used for writing data to the measurement counter and a read-modify-write instruction
(AND, OR, ADD, SUB, etc.) cannot be used.
Analog comparator
(1) To reduce current consumption, turn the analog comparator off (CMPON = "0") when it is not neces-
sary.
(2) After the analog comparator is turned on, a maximum of 3 msec is necessary until the output stabi-
lizes. Consequently, allow an adequate waiting time after turning the analog comparator on, before
reading the comparison result.
SVD circuit
(1) To obtain a stable detection result, the SVD circuit must be on for at least 500 µsec. So, to obtain the
SVD detection result, follow the programming sequence below.
1. Set SVDON to "1"
2. Maintain for 500 µsec minimum
3. Set SVDON to "0"
4. Read SVDDT
(2) The SVD circuit should normally be turned off because SVD operation increase current consumption.
Interrupt
(1) The interrupt factor flags are set when the interrupt condition is established, even if the interrupt
mask registers are set to "0".
(2) After an interrupt occurs, the same interrupt will occur again if the interrupt enabled state (I flag =
"1") is set or the RETI instruction is executed unless the interrupt factor flag is reset. Therefore, be sure
to reset (write "1" to) the interrupt factor flag in the interrupt service routine before shifting to the
interrupt enabled state.
(3) After an initial reset, all the interrupts including NMI are masked until both the stack pointers SP1
and SP2 are set with the software. Be sure to set the SP1 and SP2 in the initialize routine. Further,
when re-setting the stack pointer, the SP1 and SP2 must be set as a pair. When one of them is set, all
the interrupts including NMI are masked and interrupts cannot be accepted until the other one is set.
