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S1C63666 TECHNICAL MANUAL

EPSON

107

CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Integer Multiplier)

4.14.3 Division mode

To perform a division, set the divisor to the source register (SR) and the dividend to the destination
register (DRH and DRL), then write "1" to the calculation mode selection register (CALMD). The division
takes 10 CPU clock cycles from writing "1" to CALMD until the quotient is loaded into the low-order 8
bits (DRL) of the destination register and the remainder is loaded into the high-order 8 bits (DRH) of the
destination register. At the same time the result is loaded, the operation flags (NF, VF and ZF) are up-
dated.
However, when an overflow results (if the quotient exceeds the 8-bit range), the destination register
(DRH and DRL) does not change its contents as it maintains the dividend.
The following shows the conditions that change the operation flag states and examples of division.

N flag:

Set when the MSB of DRL is "1" and reset when it is "0".

V flag:

Set when the quotient exceeds the 8-bit range and reset when it is within the 8-bit range.

Z flag:

Set when the 8-bit value in DRL is 00H and reset when it is not 00H.

<Examples of division>

DRH/DRL (dividend) SR (divisor)

DRL (quotient) DRH (remainder)

NF VF

ZF

1A16H

64H

42H

4EH

0

0

0

332CH

64H

83H

00H

1

0

0

0000H

58H

00H

00H

0

0

1

2468H

13H

68H

24H

1

1

0

In the example of "2468H"

÷

"13H" shown above, DRH/DRL maintains the dividend because the quotient

overflows the 8-bit. To get the correct results when an overflow has occurred, perform the division with
two steps as shown below.

1. Divide the high-order 8 bits of the dividend (24H) by the divisor (13H) and then store the quotient

(01H) to memory.

DRH/DRL (dividend) SR (divisor)

DRL (quotient) DRH (remainder)

NF VF

ZF

0024H

13H

01H

11H

0

0

0

2. Keep the remainder (11H) in DRH and load the low-order 8 bits of the dividend (68H) to DRL, then

perform division again.

DRH/DRL (dividend) SR (divisor)

DRL (quotient) DRH (remainder)

NF VF

ZF

1168H

13H

EAH

0AH

1

0

0

The correct result is obtained as the quotient = 01EAH (the first and second results of DRL are merged)
and the remainder = 0AH. However, since the operation flags (NF/VF/ZF) are changed in each step, they
cannot indicate the states according to the final operation results.

Note: Make sure that the division results are correct using software as the hardware does not check.

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Summary of Contents for S1C63666

Page 1: ...Technical Manual CMOS 4 BIT SINGLE CHIP MICROCOMPUTER S1C63666 Technical Hardware S1C63666 ...

Page 2: ...uiring high level reliability such as medical products Moreover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to...

Page 3: ...istics Analog Circuit Characteristics and Power Current Consumption Oscillation Characteristics Serial Interface AC Characteristics Connecting to the Target System Differences with the actual IC Contents Explanation was revised Explanation was revised Figure 2 1 5 1 was revised Figure 2 2 1 was revised Explanation was added Explanation was revised Table 2 2 2 1 was revised Explanation was revised ...

Page 4: ......

Page 5: ...tion Package D die form F QFP B BGA Model number Model name C microcomputer digital products Product classification S1 semiconductor Development tools S5U1 C 63000 A1 1 Packing specifications 00 standard packing Version 1 Version 1 Tool type Hx ICE Ex EVA board Px Peripheral board Wx Flash ROM writer for the microcomputer Xx ROM writer peripheral board Cx C compiler package Ax Assembler package Dx...

Page 6: ......

Page 7: ...ter at initial resetting 13 2 2 4 Terminal settings at initial resetting 14 2 3 Test Terminal TEST 14 CHAPTER 3 CPU ROM RAM________________________________________ 15 3 1 CPU 15 3 2 Code ROM 15 3 3 RAM 15 3 4 Data ROM 16 CHAPTER 4 PERIPHERAL CIRCUITS AND OPERATION__________________________ 17 4 1 Memory Map 17 4 2 Power Control 25 4 2 1 Configuration of power supply circuit 25 4 2 2 Power control ...

Page 8: ... 4 8 4 Display memory 58 4 8 5 Segment option 58 4 8 6 LCD contrast adjustment 60 4 8 7 I O memory of LCD driver 61 4 8 8 Programming note 62 4 9 Clock Timer 63 4 9 1 Configuration of clock timer 63 4 9 2 Data reading and hold function 63 4 9 3 Interrupt function 64 4 9 4 I O memory of clock timer 65 4 9 5 Programming notes 66 4 10 Stopwatch Timer 67 4 10 1 Configuration of stopwatch timer 67 4 10...

Page 9: ...erter 111 4 15 1 Configuration of R f converter 111 4 15 2 Connection terminals and CR oscillation circuit 111 4 15 3 Operation of R f conversion 113 4 15 4 Interrupt function 116 4 15 5 I O memory of R f converter 118 4 15 6 Programming notes 121 4 16 Analog Comparator 122 4 16 1 Configuration of analog comparator 122 4 16 2 Analog comparator operation 122 4 16 3 I O memory of analog comparator 1...

Page 10: ... Timing Chart 147 7 8 R f Converter Characteristics 147 CHAPTER 8 PACKAGE _______________________________________________ 148 8 1 Plastic Package 148 8 2 Ceramic Package for Test Samples 149 CHAPTER 9 PAD LAYOUT ____________________________________________ 150 9 1 Diagram of Pad Layout 150 9 2 Pad Coordinates 151 APPENDIX S5U1C63000P1 MANUAL PERIPHERAL CIRCUIT BOARD FOR S1C63666 __ 152 A 1 Names a...

Page 11: ... input output 2 Serial interface 1 port 8 bit clock synchronous system LCD driver 64 segments 4 5 or 8 commons 2 Time base counter Clock timer Stopwatch timer 1 1000 sec with direct key input function Programmable timer 8 bits 3 ch or 16 bits 1 ch 8 bits 1 ch 2 Watchdog timer Built in Sound generator With envelope and 1 shot output functions R f converter 2 ch CR oscillation type 20 bit counter Mu...

Page 12: ...REF RFIN RFOUT RESET R00 R03 R10 R13 P00 P03 P10 P13 BZ BZ CMPP0 CMPM0 Core CPU S1C63000 ROM 16 384 words 13 bits System Reset Control Interrupt Generator OSC RAM 5 120 words 4 bits Data ROM 4 096 words 4 bits LCD Driver 64 SEG 8 COM Power Controller SVD Sound Generator Analog Comparator Clock Timer Stopwatch Timer Programmable Timer Counter Input Port R F Converter Serial Interface I O Port Outpu...

Page 13: ...name N C COM0 COM1 COM2 COM3 CA CB VC1 VC2 VC3 CMPP0 CMPM0 SVD VSSA RFOUT RFIN REF SEN0 SEN1 VDDA CC CD VD2 VDD VOSC OSC1 OSC2 VD1 OSC3 OSC4 VSS TEST RESET N C N C N C Pin name N C SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 N C N C N C Pin name N C N ...

Page 14: ...elected by software I O port or serial I F data output pin selected by software I O port or serial I F clock I O pin selected by software I O port or serial I F ready signal output pin selected by software I O port pins Output port pin Output port pin Output port or TOUT output pin selected by software Output port or FOUT output pin selected by software Output port pins LCD common output pin 1 4 1...

Page 15: ...ection 2 2 1 Reset terminal RESET for details 6 I O port pull down resistor The mask option is used to select whether the pull down resistor working in the input mode is supplemented to the I O ports or not It is possible to select for each bit of the input ports Refer to Section 4 7 2 Mask option for details 7 Output specification of the output port Either complementary output or P channel open d...

Page 16: ...ailable in each option item as indicated in the option list Select the specifica tions that meet the target system and check the appropriate box Be sure to record the specifications for unused functions too 1 OSC1 SYSTEM CLOCK 1 Crystal 2 OSC3 SYSTEM CLOCK 1 CR built in R 2 CR external R 3 Ceramic 3 SVD EXTERNAL VOLTAGE DETECTION 1 Not Use 2 Use 4 INPUT PORT PULL DOWN RESISTOR K00 1 With Resistor ...

Page 17: ... Complementary 2 Pch OpenDrain P02 1 Complementary 2 Pch OpenDrain P03 1 Complementary 2 Pch OpenDrain P10 1 Complementary 2 Pch OpenDrain P11 1 Complementary 2 Pch OpenDrain P12 1 Complementary 2 Pch OpenDrain P13 1 Complementary 2 Pch OpenDrain 9 MULTIPLE KEY ENTRY RESET COMBINATION 1 Not Use 2 Use K00 K01 3 Use K00 K01 K02 4 Use K00 K01 K02 K03 10 MULTIPLE KEY ENTRY RESET TIME AUTHORIZE 1 Not U...

Page 18: ... H L D COM6 H L D SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG ...

Page 19: ... OSC3 and internal circuits high speed operation LCD driver Power supply Voltage regulator for OSC1 oscillation circuit Low speed operation voltage regulator High speed operation voltage regulator LCD system voltage circuit Output voltage VOSC VD1L VD3 VC1 VC3 Note Do not drive external loads with the output voltage from the internal power supply circuits See Chapter 7 Electrical Characteristics f...

Page 20: ... OSC1 and OSC3 built in Use OSC1 clock for normal operation and switch to OSC3 using software when high speed operation is necessary When switching the clock the operating voltage VD1 must be switched using software to stabilize the operation of the oscillation circuit and internal circuits In low speed operation VD1L generated by the low speed operation voltage regulator is used as VD1 In high sp...

Page 21: ...tus is the halver mode for reducing current consumption during HALT or low speed operation At initial reset the low speed operation voltage regulator and LCD system voltage circuit are set in the normal mode using VDD When necessary switch to the halver mode using software The halver mode supports only low speed operation using the OSC1 clock and cannot be set during high speed operation using the...

Page 22: ...that the initial reset is released by setting the reset terminal to a low level VSS and the CPU starts operation The reset input signal is maintained by the RS latch and becomes the internal initial reset signal The RS latch is designed to be released by a 2 Hz signal high that is divided by the OSC1 clock Therefore in normal operation a maximum of 250 msec when fOSC1 32 768 kHz is needed until th...

Page 23: ...1 Stack pointer SP2 Zero flag Carry flag Interrupt flag Extension flag Queue register CPU core Symbol A B EXT X Y PC SP1 SP2 Z C I E Q Number of bits 4 4 8 16 16 16 8 8 1 1 1 1 16 Setting value Undefined Undefined Undefined Undefined Undefined 0110H Undefined Undefined Undefined Undefined 0 0 Undefined Name RAM Display memory Other peripheral circuits Peripheral circuits Number of bits 4 4 Setting...

Page 24: ... the shared terminal settings Table 2 2 4 1 List of shared terminal settings Terminal name R00 R01 R02 R03 R10 R13 P00 P03 P10 P11 P12 P13 Terminal status at initial reset R00 LOW output R01 LOW output R02 LOW output R03 LOW output R10 R13 LOW output P00 P03 Input pulled down P10 Input pulled down P11 Input pulled down P12 Input pulled down P13 Input pulled down Special output TOUT FOUT TOUT FOUT ...

Page 25: ...s 0000H to 01FFH on the data memory map Addresses 0100H to 01FFH are 4 bit 16 bit data accessible areas and in other areas it is only possible to access 4 bit data When programming keep the following points in mind 1 Part of the RAM area is used as a stack area for subroutine call and register evacuation so pay attention not to overlap the data area and stack area 2 The S1C63000 core CPU handles t...

Page 26: ...bit data 0000H 00FFH 0100H 01FFH 0200H 13FFH 4 bits 4 bit access area SP2 stack area 4 bit access area Data area 4 16 bit access area SP1 stack area Fig 3 3 1 Configuration of data RAM 3 4 Data ROM The data ROM is a mask ROM for loading various static data such as a character generator and has a capacity of 4 096 words 4 bits The data ROM is assigned to addresses 8000H to 8FFFH on the data memory ...

Page 27: ...word data ROM 160 word display memory and 92 word peripheral I O memory Figure 4 1 1 shows the overall memory map of the S1C63666 and Table 4 1 1 the peripheral circuits I O space memory maps 0000H 1400H 8000H 9000H F000H FF00H FFFFH RAM area Unused area Unused area Data ROM area I O memory area Display memory area Unused area Peripheral I O area F000H F0A0H FF00H FFFFH Fig 4 1 1 Memory map Note M...

Page 28: ...2 30 4 2 45 5 2 60 6 2 75 7 2 90 SVDS2 0 Voltage V FOUT output enable Stopwatch direct input switch 0 K00 Run Stop K01 Lap 1 K00 Lap K01 Run Stop FOUT frequency selection 0 fOSC1 64 1 fOSC1 8 2 fOSC1 3 fOSC3 FOFQ1 0 Frequency FF20H SIK03 SIK02 SIK01 SIK00 R W SIK03 SIK02 SIK01 SIK00 0 0 0 0 Enable Enable Enable Enable Disable Disable Disable Disable K00 K03 interrupt selection register FF21H K03 K...

Page 29: ...purpose register when SIF is selected FF45H PUL13 PUL12 PUL11 PUL10 R W PUL13 PUL12 PUL11 PUL10 1 1 1 1 On On On On Off Off Off Off P13 pull down control register functions as a general purpose register when SIF slave is selected P12 pull down control register ESIF 0 functions as a general purpose register when SIF master is selected SCLK I pull down control register when SIF slave is selected P11...

Page 30: ...ow Low Low MSB Serial I F transmit receive data high order 4 bits LSB W R W R FF74H 0 0 TMRST TMRUN 0 3 0 3 TMRST 3 TMRUN 2 2 Reset 0 Reset Run Invalid Stop Unused Unused Clock timer reset writing Clock timer Run Stop R FF75H TM3 TM2 TM1 TM0 TM3 TM2 TM1 TM0 0 0 0 0 Clock timer data 16 Hz Clock timer data 32 Hz Clock timer data 64 Hz Clock timer data 128 Hz R FF76H TM7 TM6 TM5 TM4 TM7 TM6 TM5 TM4 0...

Page 31: ...MD 0 0 0 0 Negative Overflow Zero Run Div Positive No No Stop Mult Negative flag Overflow flag Zero flag Operation status reading Calculation mode selection writing DRH3 DRH2 DRH1 DRH0 2 2 2 2 High order 8 bit destination register low order 4 bits LSB R W FF84H DRH3 DRH2 DRH1 DRH0 DRH7 DRH6 DRH5 DRH4 2 2 2 2 MSB High order 8 bit destination register high order 4 bits R W FF85H DRH7 DRH6 DRH5 DRH4 ...

Page 32: ...mer 2 Run Stop W R W R W FFC5H PTPS21 PTPS20 PTRST2 PTRUN2 0 1 1 1 1 4 2 1 32 3 1 256 PTPS21 20 Division ratio R W FFC0H MOD16 EVCNT FCSEL PLPOL 1 0 0 3 CHSEL1 CHSEL0 PTOUT 2 0 0 0 On Off Unused TOUT output selection TOUT output control R R W FFC1H 0 CHSEL1 CHSEL0 PTOUT 0 Timer 0 1 Timer 1 2 Timer 2 CHSEL1 0 Timer 0 3 CKSEL2 CKSEL1 CKSEL0 2 0 0 0 OSC3 OSC3 OSC3 OSC1 OSC1 OSC1 Unused Prescaler 2 so...

Page 33: ...01 PTD00 0 0 0 0 MSB Programmable timer 0 data low order 4 bits LSB R FFCCH PTD03 PTD02 PTD01 PTD00 PTD07 PTD06 PTD05 PTD04 0 0 0 0 MSB Programmable timer 0 data high order 4 bits LSB R FFCDH PTD07 PTD06 PTD05 PTD04 PTD13 PTD12 PTD11 PTD10 0 0 0 0 MSB Programmable timer 1 data low order 4 bits LSB R FFCEH PTD13 PTD12 PTD11 PTD10 PTD17 PTD16 PTD15 PTD14 0 0 0 0 MSB Programmable timer 1 data high or...

Page 34: ...s W Reset R No W Invalid Interrupt factor flag Clock timer 1 Hz Interrupt factor flag Clock timer 2 Hz Interrupt factor flag Clock timer 8 Hz Interrupt factor flag Clock timer 32 Hz FFF3H 0 0 0 IK0 R R W 0 3 0 3 0 3 IK0 2 2 2 0 R Yes W Reset R No W Invalid Unused Unused Unused Interrupt factor flag K00 K03 FFF4H 0 0 0 IK1 R R W 0 3 0 3 0 3 IK1 2 2 2 0 R Yes W Reset R No W Invalid Unused Unused Unu...

Page 35: ...generate the VD1L voltage 1 25 V Typ for driving the internal logic circuits The VD1L voltage is used as the VD1 operating voltage of the CPU and internal logic circuits when they are driven with the OSC1 clock 32 kHz VD1 should be switched using software according to the operating clock High speed operation voltage regulator The high speed operation voltage regulator generates the VD3 voltage 2 0...

Page 36: ... logic operating voltage VD1L VDC0 0 CPU system clock OSC1 CLKCHG 0 OSC3 oscillation circuit OFF OSCC 0 Setting halver mode The low speed operation voltage regulator and the LCD system voltage circuit can be set into the halver mode independently Setting the low speed operation voltage regulator The low speed operation voltage regulator can be set into the halver mode under the conditions below Wh...

Page 37: ...3 I O memory for power control Table 4 2 3 1 shows the I O address and the control bits for power control Table 4 2 3 1 Power control bits Address Comment D3 D2 Register D1 D0 Name Init 1 1 0 FF00H VDC3 VDC2 VDC1 VDC0 R W VDC3 VDC2 VDC1 VDC0 0 0 0 0 1 2VDD 1 2VDD On VD3 VDD VDD Off VD1L LCD system voltage regulator power source switch Low speed operation voltage regulator power source switch High ...

Page 38: ...n voltage regulator enters the normal mode and operates with the supply voltage VDD At initial reset the hardware sets the normal mode and this register is set to 0 VDC3 LCD system voltage circuit power control register FF00H D3 Sets the LCD system voltage circuit to the halver mode When 1 is written Halver mode driven with 1 2 VDD When 0 is written Normal mode driven with VDD Reading Valid When 1...

Page 39: ...ode make sure that the supply voltage is 2 4 V or higher using the SVD circuit before writing 1 to VDC2 Furthermore switch the CPU clock to OSC1 2 When setting the LCD system voltage circuit to the halver mode make sure that the supply voltage is 2 4 V or higher using the SVD circuit before writing 1 to VDC3 Furthermore set the VC1 voltage contrast to 1 13 V or lower LC register 6 or less ...

Page 40: ... bit binary counter and generates the non maskable interrupt when the last stage of the counter 0 25 Hz overflows Watchdog timer reset processing in the program s main routine enables detection of program overrun such as when the main routine s watchdog timer processing is bypassed Ordinarily this routine is incorporated where periodic processing takes place just as for the timer interrupt routine...

Page 41: ...hen 0 is written Disabled Reading Valid When 1 is written to the WDEN register the watchdog timer starts count operation When 0 is written the watchdog timer does not count and does not generate the interrupt NMI At initial reset this register is set to 1 WDRST Watchdog timer reset FF07H D0 Resets the watchdog timer When 1 is written Watchdog timer is reset When 0 is written No operation Reading A...

Page 42: ...High speed operation voltage regulator Voltage regulator for OSC1 oscillation circuit Oscillation circuit control signal CPU clock selection signal To CPU To peripheral circuits Clock switch OSC3 oscillation circuit OSC1 oscillation circuit Operating voltage selection signal Divider Fig 4 4 1 1 Oscillation system block diagram 4 4 2 OSC1 oscillation circuit The OSC1 crystal oscillation circuit gen...

Page 43: ...R CR VSS CGC CDC Ceramic OSC4 OSC3 R RDC To CPU and some peripheral circuits Oscillation circuit control signal FC To CPU and some peripheral circuits Oscillation circuit control signal a CR oscillation circuit external R type CCR OSC3 OSC4 R CR Fig 4 4 3 1 OSC3 oscillation circuit As shown in Figure 4 4 3 1 the CR oscillation circuit external R type can be configured simply by connecting the resi...

Page 44: ...mal mode before switching the operating voltage OSC1 OSC3 1 Set VDC2 to 0 low speed operation voltage regulator halver mode normal mode 2 Set VDC1 to 1 high speed operation voltage regulator off on 3 Set VDC0 to 1 internal logic operating voltage VD1L VD3 4 Wait 2 5 msec or more 5 Set OSCC to 1 OSC3 oscillation off on 6 Wait 5 msec or more 7 Set CLKCHG to 1 CPU clock OSC1 OSC3 OSC3 OSC1 1 Set CLKC...

Page 45: ...started When the low speed operation voltage regulator is in the halver mode return it to the normal mode before switching to VD3 When 0 is written to VDC0 the internal operating voltage is switched to VD1L Stop the OSC3 oscillation before switching to VD1L At initial reset this register is set to 0 OSCC OSC3 oscillation control register FF01H D2 Turns the OSC3 oscillation circuit on and off When ...

Page 46: ...SC1 to OSC3 do this after a minimum of 5 msec have elapsed since the OSC3 oscillation went on Further the oscillation stabilization time varies depending on the external oscillator characteristics and conditions of use so allow ample margin when setting the wait time 3 When switching the clock form OSC3 to OSC1 use a separate instruction for switching the OSC3 oscillation off An error in the CPU o...

Page 47: ... for slide switch input and interfacing with other LSIs The K00 and K01 input ports can also be used as the Run Stop and Lap direct inputs for the stopwatch timer and the K13 port can also be used as the event counter input for the programmable timer 4 5 2 Interrupt function All eight bits of the input ports K00 K03 K10 K13 provide the interrupt function The conditions for issuing an interrupt can...

Page 48: ...of an interrupt for K00 K03 Interrupt selection register SIK03 1 SIK02 1 SIK01 1 SIK00 0 Input port 1 Initial value Interrupt generation K03 1 K02 0 K01 1 K00 0 Input comparison register KCP03 1 KCP02 0 KCP01 1 KCP00 0 With the above setting the interrupt of K00 K03 is generated under the following condition 2 K03 1 K02 0 K01 1 K00 1 3 K03 0 K02 0 K01 1 K00 1 4 K03 0 K02 1 K01 1 K00 1 Because K00 ...

Page 49: ... K10 K13 input port data FF26H KCP13 KCP12 KCP11 KCP10 R W KCP13 KCP12 KCP11 KCP10 1 1 1 1 K10 K13 input comparison register FFE3H 0 0 0 EIK0 R R W 0 3 0 3 0 3 EIK0 2 2 2 0 Enable Mask Unused Unused Unused Interrupt mask register K00 K03 FFE4H 0 0 0 EIK1 R R W 0 3 0 3 0 3 EIK1 2 2 2 0 Enable Mask Unused Unused Unused Interrupt mask register K10 K13 FFF3H 0 0 0 IK0 R R W 0 3 0 3 0 3 IK0 2 2 2 0 R Y...

Page 50: ...gisters At initial reset these registers are set to 1 EIK0 K0 input interrupt mask register FFE3H D0 EIK1 K1 input interrupt mask register FFE4H D0 Masking the interrupt of the input port can be selected with these registers When 1 is written Enable When 0 is written Mask Reading Valid With these registers masking of the input port interrupt can be selected for each of the two systems K00 K03 K10 ...

Page 51: ...are needs to be taken of the key scan during key matrix configuration Make this waiting time the amount of time or more calculated by the following expression 10 C R C terminal capacitance 5 pF parasitic capacitance pF R pull down resistance 375 kΩ Max 2 After an interrupt occurs the same interrupt will occur again if the interrupt enabled state I flag 1 is set or the RETI instruction is executed ...

Page 52: ...y the software At initial reset these are all set to the general purpose output port Table 4 6 1 1 shows the setting of the output terminals by function selection Table 4 6 1 1 Function setting of output terminals Terminal name R00 R01 R02 R03 R10 R13 Terminal status at initial reset R00 Low output R01 Low output R02 Low output R03 Low output R10 R13 Low output Special output TOUT FOUT R00 R00 R01...

Page 53: ...hows the configuration of the R02 and R03 output ports Table 4 6 4 1 Special output Terminal R03 R02 Special output FOUT TOUT Output control register FOUTE PTOUT Data bus Register PTOUT Register R02 TOUT R02 TOUT Register FOUTE Register R03 Register R03HIZ Register R02HIZ FOUT R03 FOUT Fig 4 6 4 1 Configuration of R02 and R03 output ports At initial reset the output port data register is set to 0 ...

Page 54: ...tput from the oscillation circuit or a clock that the fOSC1 clock has divided in the internal circuit and can be used to provide a clock signal to an external device To output the FOUT signal fix the R03 register at 1 and the R03HIZ register at 0 and turn the signal on and off using the FOUTE register The frequency of the output clock may be selected from among 4 types shown in Table 4 6 4 2 by se...

Page 55: ...OUT 0 Fix at 1 when TOUT is used R01 output port data R00 output port data FF32H 0 0 0 R1HIZ R R W 0 3 0 3 0 3 R1HIZ 2 2 2 0 Hi Z Output Unused Unused Unused R10 R13 Hi Z control FF33H R13 R12 R11 R10 R W R13 R12 R11 R10 0 0 0 0 High High High High Low Low Low Low R10 R13 output port data 0 3 CHSEL1 CHSEL0 PTOUT 2 0 0 0 On Off Unused TOUT output selection TOUT output control R R W FFC1H 0 CHSEL1 C...

Page 56: ...Valid By writing 1 to the FOUTE register when the R03 register has been set to 1 and the R03HIZ register has been set to 0 the FOUT signal is output from the R03 terminal When 0 is written the R03 termi nal goes low VSS When using the R03 output port for DC output fix this register at 0 At initial reset this register is set to 0 FOFQ0 FOFQ1 FOUT frequency selection register FF06H D0 D1 Selects a f...

Page 57: ... VSS level the same as the DC output if 0 is written to the R02 and R03 registers when the special output has been selected Be aware that the output terminal shifts into high impedance status when 1 is written to the high impedance control register R02HIZ R03HIZ 2 A hazard may occur when the FOUT signal and the TOUT signal are turned on and off 3 When fOSC3 is selected for the FOUT signal frequenc...

Page 58: ...e terminals are all set to the I O port Table 4 7 1 1 shows the setting of the input output terminals by function selection Table 4 7 1 1 Function setting of input output terminals Terminal P00 P03 P10 P11 P12 P13 Terminal status at initial reset P00 P03 Input pull down P10 Input pull down P11 Input pull down P12 Input pull down P13 Input pull down Serial I F Master Slave P00 P03 P00 P03 SIN I SIN...

Page 59: ...rite 1 is to the I O control register When an I O port is set to output mode it works as an output port it outputs a high level VDD when the port output data is 1 and a low level VSS when the port output data is 0 If perform the read out in each mode when output mode the register value is read out and when input mode the port value is read out At initial reset the I O control registers are set to ...

Page 60: ... register when SIF is selected FF45H PUL13 PUL12 PUL11 PUL10 R W PUL13 PUL12 PUL11 PUL10 1 1 1 1 On On On On Off Off Off Off P13 pull down control register functions as a general purpose register when SIF slave is selected P12 pull down control register ESIF 0 functions as a general purpose register when SIF master is selected SCLK I pull down control register when SIF slave is selected P11 pull d...

Page 61: ...written as the port data the port terminal goes high VDD and when 0 is written the terminal goes low VSS Port data can be written also in the input mode When reading data When 1 is read High level When 0 is read Low level The terminal voltage level of the I O port is read out When the I O port is in the input mode the voltage level being input to the port terminal can be read out in the output mod...

Page 62: ...to enable in 1 bit units The pull down resistor is included into the ports selected by mask option By writing 1 to the pull down control register the corresponding I O ports are pulled down during input mode while writing 0 disables the pull down function At initial reset these registers are all set to 1 so the pull down function is enabled The pull down control registers of the ports in which the...

Page 63: ...el VDD VC3 3 External power supply 1 2 bias for 3 0 V panel VDD VC3 VC1 VC2 static drive function is available Note that the power control using the LPWR register is necessary even if an external power supply is used SEG output ports that are set for DC output by the mask option operate same as the output R port regardless of the power on off control by the LPWR register 4 8 3 Control of LCD displ...

Page 64: ...HERAL CIRCUITS AND OPERATION LCD Driver COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG63 VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC2 VC1 VC2 VC1 Not lit Lit LCD lighting status COM0 COM1 COM2 COM3 SEG0 63 Frame Fig 4 8 3 1 Dynamic drive waveform for 1 4 duty ...

Page 65: ...AL CIRCUITS AND OPERATION LCD Driver COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG63 VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC2 VC1 VC2 VC1 Not lit Lit LCD lighting status COM0 COM1 COM2 COM3 COM4 SEG0 63 Frame Fig 4 8 3 2 Dynamic drive waveform for 1 5 duty ...

Page 66: ...CIRCUITS AND OPERATION LCD Driver COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 SEG63 VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC2 VC1 Not lit Lit LCD lighting status Frame COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 SEG0 63 Fig 4 8 3 3 Dynamic drive waveform for 1 8 duty ...

Page 67: ...nding to the SEG terminal the SEG terminal outputs a static on waveform When all the COM0 to COM7 bits are set to 0 the SEG terminal outputs a dynamic off waveform Figure 4 8 3 4 shows the static drive waveform COM 0 7 Frame frequency VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS SEG 0 63 LCD lighting status COM0 COM1 COM7 SEG0 63 Not lit Lit Fig 4 8 3 4 Static drive waveform Note To use the sta...

Page 68: ...t This makes design easy by increasing the degree of freedom with which the liquid crystal panel can be designed Figure 4 8 5 1 shows an example of the relationship between the LCD segments on the panel and the display memory for the case of 1 4 duty a f g e d p c SEG10 SEG11 Common 0 Common 1 Common 2 F060H F061H Address d p D3 c g D2 b f D1 a e D0 Data Display memory allocation SEG10 SEG11 61 D1...

Page 69: ... L D COM4 H L D COM5 H L D COM6 H L D SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output S DC output C N SEG output ...

Page 70: ...ing to VC1 Table 4 8 6 1 LCD contrast No 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 LC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VC1 V 0 95 0 98 1 01 1 04 1 07 1 10 1 13 1 16 1 19 1 22 1 25 1 28 1 31 1 34 1 37 1 40 Contrast light dark Do not set VC1 to 1 16 V or more LC 7 or more when the LCD system volta...

Page 71: ...0 1 2 3 4 5 6 7 8 9 A B C D E F F000H F010H F020H F030H F040H F050H F060H F070H F080H F090H Display memory 160 words 4 bits R W Fig 4 8 7 1 Display memory map LPWR LCD power control on off register FF60H D0 Turns the LCD system voltage circuit on and off When 1 is written On When 0 is written Off Reading Valid When 1 is written to the LPWR register the LCD system voltage circuit goes on and genera...

Page 72: ... register FF61H D2 Fade outs the all LCD segments When 1 is written All LCD segments fade out When 0 is written Normal display Reading Valid By writing 1 to the ALOFF register all the LCD segments go off and when 0 is written it returns to normal display This function outputs an off waveform to the SEG terminals and does not affect the content of the display memory ALON FF61H D1 has priority over ...

Page 73: ...0 TM0 128 Hz D1 TM1 64 Hz D2 TM2 32 Hz D3 TM3 16 Hz FF76H D0 TM4 8 Hz D1 TM5 4 Hz D2 TM6 2 Hz D3 TM7 1 Hz Since the clock timer data has been allocated to two addresses a carry is generated from the low order data within the count TM0 TM3 128 16 Hz to the high order data TM4 TM7 8 1 Hz When this carry is generated between the reading of the low order data and the high order data a content combinin...

Page 74: ...nterrupt request Bit D0 D1 D2 D3 D0 D1 D2 D3 Frequency Clock timer timing chart 128 Hz 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz Fig 4 9 3 1 Timing chart of clock timer As shown in Figure 4 9 3 1 interrupt is generated at the falling edge of the frequencies 32 Hz 8 Hz 2 Hz 1 Hz At this time the corresponding interrupt factor flag IT0 IT1 IT2 IT3 is set to 1 Selection of whether to mask the separate in...

Page 75: ...lock timer 32 Hz 1 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read TM0 TM7 Timer data FF75H FF76H The 128 1 Hz timer data of the clock timer can be read out with these registers These eight bits are read only and writing operations are invalid By reading the low order data FF75H the high order data FF76H is held until reading or for 0 48 1 5 msec one of short...

Page 76: ... factor flags IT0 IT1 IT2 IT3 correspond to the clock timer interrupts of the respective frequencies 32 Hz 8 Hz 2 Hz 1 Hz The software can judge from these flags whether there is a clock timer interrupt However even if the interrupt is masked the flags are set to 1 at the falling edge of the signal These flags are reset to 0 by writing 1 to them After an interrupt occurs the same interrupt will oc...

Page 77: ...arate timer from the clock timer In particular digital watch stopwatch functions can be realized easily with software 4 10 2 Counter and prescaler The stopwatch timer is configured of four bit BCD counters SWD0 3 SWD4 7 and SWD8 11 The counter SWD0 3 at the stage preceding the stopwatch timer has a 1 000 Hz signal generated by the prescaler for the input clock It counts up every 1 1 000 sec and ge...

Page 78: ...leased when SWD8 11 1 10 sec reading is completed Therefore data should be read in order of SWD0 3 SWD4 7 SWD8 11 If SWD4 7 or SWD8 11 is first read when data have not been held the hold function does not work and data in the counter is directly read out When data that has not been held is read in the stopwatch timer RUN status you cannot judge whether it is correct or not The stopwatch timer has ...

Page 79: ...nd is maintained as is When the stopwatch timer is reset in the RUN status counting restarts from count 000 Also in the STOP status the reset data 000 is maintained until the next RUN 4 10 5 Direct input function and key mask The stopwatch timer has a direct input function that can control the RUN STOP and LAP operation of the stopwatch timer by external key input This function is set by writing 1...

Page 80: ...ewal flag is set renewed data is held in the capture buffer So it is necessary to read from SWD0 3 again The stopwatch timer sets the 1 Hz interrupt factor flag ISW1 to 1 when requiring a carry up to 1 sec digit by an SWD8 11 overflow If the capture buffer shifts into hold status when SWD0 3 is read or when LAP is input while the 1 Hz interrupt factor flag ISW1 is set to 1 the lap data carry up re...

Page 81: ...or LAP inputs become invalid in the following status 1 The RUN or LAP key is pressed when one or more keys that are included in the selected combina tion here in after referred to as mask are held down 2 The RUN or LAP key has been pressed when the mask is released fOSC1 32 1 024 Hz Direct RUN LAP input Key mask valid invalid invalid invalid Fig 4 10 5 4 Operation of key mask RUN or LAP inputs bec...

Page 82: ...D3 D0 D1 D2 D3 Address Register Stopwatch timer SWD0 3 timing chart FF7AH 1 1 000 sec BCD D0 D1 D2 D3 Address Register Stopwatch timer SWD4 7 timing chart Address Register Stopwatch timer SWD8 11 timing chart Fig 4 10 6 1 Timing chart for counters As shown in Figure 4 10 6 1 the interrupts are generated by the overflow of their respective counters 9 changing to 0 Also at this time the correspondin...

Page 83: ...LAP The direct RUN and LAP functions use the K00 and K01 ports Therefore the direct input interrupt and the K00 K03 inputs interrupt may generate at the same time depending on the interrupt condi tion setting for the input port K00 K03 Consequently when using the direct input interrupt set the interrupt selection registers SIK00 and SIK01 to 0 so that the input interrupt does not generate by K00 a...

Page 84: ...writing FFE6H EIRUN EILAP EISW1 EISW10 R W EIRUN EILAP EISW1 EISW10 0 0 0 0 Enable Enable Enable Enable Mask Mask Mask Mask Interrupt mask register Stopwatch direct RUN Interrupt mask register Stopwatch direct LAP Interrupt mask register Stopwatch timer 1 Hz Interrupt mask register Stopwatch timer 10 Hz FFF6H IRUN ILAP ISW1 ISW10 R W IRUN ILAP ISW1 ISW10 0 0 0 0 R Yes W Reset R No W Invalid Interr...

Page 85: ...tatuses are input to the stopwatch timer as the RUN STOP and LAP inputs according to this selection At initial reset this register is set to 0 DKM0 DKM2 Direct key mask selection register FF78H D0 D2 Selects a combination of the key inputs for concurrence judgment with RUN and LAP inputs when the direct input function is set Table 4 10 7 2 Key mask selection DKM2 0 0 0 0 1 1 1 1 DKM1 0 0 1 1 0 0 1...

Page 86: ...t required Writing Invalid If the capture buffer shifts into hold status while the 1 Hz interrupt factor flag ISW1 is set to 1 LCURF is set to 1 to indicate that a carry up to 1 sec digit is required When performing a processing such as a LAP input preceding with 1 Hz interrupt processing read this flag before processing and check whether carry up is needed or not This flag is renewed set reset ev...

Page 87: ...upt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state At initial reset these flags are set to 0 4 10 8 Programming notes 1 The interrupt factor flag should be reset after resetting the stopwatch timer 2 Be sure to data reading in the order of SWD0 3 SWD4 7 SWD8 11 3 When data that is ...

Page 88: ...source for the serial interface timer 2 underflow is used and it is possible to set the transfer rate Reload data register RLD00 RLD07 Data buffer PTD00 PTD07 PTRUN0 FCSEL PLPOL Timer 0 PTPS00 PTPS01 8 bit down counter Prescaler Selector CKSEL0 Timer 0 Run Stop Clock control circuit Timer function setting Pulse polarity setting Prescaler setting Under flow signal Data buffer PTD20 PTD27 Timer 2 PT...

Page 89: ...s counting This control RUN STOP does not affect the counter data The counter maintains its data while stopped and can restart counting continuing from that data The counter data can be read via the data buffer PTDx0 PTDx7 in optional timing However the counter has the data hold function the same as the clock timer that holds the high order data PTDx4 PTDx7 when the low order data PTDx0 PTDx3 is r...

Page 90: ...from among 4 types This selection is done using the prescaler division ratio selection register PTPSx0 PTPSx1 Table 4 11 3 1 shows the correspondence between the setting value and the division ratio Table 4 11 3 1 Selection of prescaler division ratio PTPSx1 1 1 0 0 PTPSx0 1 0 1 0 Prescaler division ratio Source clock 256 Source clock 32 Source clock 4 Source clock 1 By writing 1 to the PTRUNx reg...

Page 91: ...ction 4 11 2 Basic count operation for basic operation and control 4 11 5 16 bit timer timer 0 timer 1 Timers 0 and 1 can be used as a 16 bit timer To use the 16 bit timer write 1 to the timer 0 16 bit mode selection register MOD16 The 16 bit timer is configured with timer 0 for low order byte and timer 1 for high order byte as shown in Figure 4 11 5 1 Reload data register RLD00 RLD07 Data buffer ...

Page 92: ...tion register CHSEL0 CHSEL1 Table 4 11 7 1 Selecting a timer for TOUT output CHSEL1 1 0 0 CHSEL0 1 0 TOUT output timer Timer 2 Timer 1 Timer 0 Select timer 1 when generating the TOUT signal from the 16 bit timer output The TOUT signal can be output from the R02 output port terminal Programmable clocks can be supplied to external devices Figure 4 11 7 1 shows the configuration of the output port R0...

Page 93: ... timer 2 into RUN state PTRUN2 1 It is not necessary to control with the PTOUT register PTRUN2 Timer 2 underflow Source clock for serial I F Fig 4 11 8 1 Synchronous clock of serial interface A setting value for the RLD2x register according to a transfer rate is calculated by the following expres sion RLD2x fosc 2 bps division ratio of the prescaler 1 fosc Oscillation frequency OSC1 OSC3 bps Trans...

Page 94: ...3 1 256 PTPS21 20 Division ratio R W FFC0H MOD16 EVCNT FCSEL PLPOL 1 0 0 3 CHSEL1 CHSEL0 PTOUT 2 0 0 0 On Off Unused TOUT output selection TOUT output control R R W FFC1H 0 CHSEL1 CHSEL0 PTOUT 0 Timer 0 1 Timer 1 2 Timer 2 CHSEL1 0 Timer 0 3 CKSEL2 CKSEL1 CKSEL0 2 0 0 0 OSC3 OSC3 OSC3 OSC1 OSC1 OSC1 Unused Prescaler 2 source clock selection Prescaler 1 source clock selection Prescaler 0 source clo...

Page 95: ...ce clock selection register FFC2H D0 CKSEL1 Prescaler 1 source clock selection register FFC2H D1 CKSEL2 Prescaler 2 source clock selection register FFC2H D2 Selects the source clock of the prescaler When 1 is written OSC3 clock When 0 is written OSC1 clock Reading Valid The source clock for the prescaler is selected from OSC1 or OSC3 When 0 is written to the CKSELx register the OSC1 clock is selec...

Page 96: ...e rejector When 0 is written Without noise rejector Reading Valid When 1 is written to the FCSEL register the noise rejector is used and counting is done by an external clock K13 with 0 98 msec or more pulse width The noise rejector allows the counter to input the clock at the second falling edge of the internal 2 048 Hz signal after changing the input level of the K13 input port terminal Conseque...

Page 97: ...ting operation is invalid At initial reset these counter data are set to 00H PTRST0 Timer 0 reset reload FFC3H D1 PTRST1 Timer 1 reset reload FFC4H D1 PTRST2 Timer 2 reset reload FFC5H D1 Resets the timer and presets reload data to the counter When 1 is written Reset When 0 is written No operation Reading Always 0 By writing 1 to PTRSTx the reload data in the reload register RLDx0 RLDx7 is preset ...

Page 98: ...r to mask the programmable timer interrupt or not When 1 is written Enabled When 0 is written Masked Reading Valid The timer x interrupt can be masked individually by the interrupt mask registers EIPTx At initial reset these registers are set to 0 IPT0 Timer 0 interrupt factor flag FFF1H D0 IPT1 Timer 1 interrupt factor flag FFF1H D1 IPT2 Timer 2 interrupt factor flag FFF1H D2 These flags indicate...

Page 99: ...t least 5 msec from turning the circuit ON until the oscillation stabilizes Therefore allow an adequate interval from turning the OSC3 oscillation circuit ON to starting the programmable timer Refer to Section 4 4 Oscillation Circuit for the control and notes of the OSC3 oscillation circuit At initial reset the OSC3 oscillation circuit is set in the off state 5 After an interrupt occurs the same i...

Page 100: ...nal which indicates whether or not the serial interface is available to transmit or receive can be output to the SRDY terminal SD0 SD7 SIN P10 SCLK or SCLK P12 SCS0 SCS1 Output latch Serial I F interrupt control circuit Interrupt request SOUT P11 SRDY or SRDY P13 SCTRG Serial I F activating circuit fOSC1 Serial clock counter Serial clock selector Serial clock generator Shift register 8 bits Progra...

Page 101: ... is assumed that positive polarity SCLK SRDY has been selected 4 12 3 Master mode and slave mode of serial interface The serial interface of the S1C63666 has two types of operation mode master mode and slave mode The master mode uses an internal clock as the synchronous clock for the built in shift register and outputs this internal clock from the SCLK P12 terminal to control the external slave si...

Page 102: ...3H and writing 1 to SCTRG bit FF70H D1 it synchronizes with the synchronous clock and the serial data is output to the SOUT P11 terminal The synchronous clock used here is as follows in the master mode internal clock which is output to the SCLK P12 terminal while in the slave mode external clock which is input from the SCLK P12 terminal Shift timing of serial data is as follows When positive polar...

Page 103: ...0 SD7 by software Serial data input output permutation The S1C63666 allows the input output permutation of serial data to be selected by the SDP register FF71H D3 as to either LSB first or MSB first The block diagram showing input output permutation in case of LSB first and MSB first is provided in Figure 4 12 4 1 The SDP register should be set before setting data to SD0 SD7 SIN SIN Address FF73H ...

Page 104: ...e mode SCTRG W SCTRG R SCLK SIN 8 bit shift register SOUT ISIF SRDY Slave mode b When SCPS 0 Fig 4 12 4 2 Serial interface timing chart when synchronous clock is positive polarity SCLK SCTRG W SCTRG R SCLK SIN 8 bit shift register SOUT ISIF SRDY Slave mode SCTRG W SCTRG R SCLK SIN 8 bit shift register SOUT ISIF SRDY Slave mode b When SCPS 0 Fig 4 12 4 3 Serial interface timing chart when synchrono...

Page 105: ...data high order 4 bits LSB SCS1 0 Clock SCS1 0 Clock FF71H SDP SCPS SCS1 SCS0 R W SDP SCPS SCS1 SCS0 0 0 0 0 MSB first LSB first Serial I F data input output permutation Serial I F clock phase selection Negative polarity mask option Positive polarity mask option Serial I F clock mode selection FF70H 0 ESOUT SCTRG ESIF R R W 0 3 ESOUT SCTRG ESIF 2 0 0 0 Enable Trigger Run SIF Disable Invalid Stop I...

Page 106: ...n register FF71H D0 D1 Selects the synchronous clock SCLK for the serial interface Table 4 12 5 2 Synchronous clock selection SCS1 1 1 0 0 SCS0 1 0 1 0 Mode Master mode Slave mode Synchronous clock OSC1 OSC1 2 Programmable timer External clock The maximum clock is limited to 1 MHz Synchronous clock SCLK is selected from among the above 4 types 3 types of internal clock and external clock When the ...

Page 107: ...o SCTRG The internal circuit of the serial interface is initiated through data writ ing reading on data registers SD0 SD7 In addition be sure to enable the serial interface with the ESIF register before setting the trigger Supply trigger only once every time the serial interface is placed in the RUN state Refrain from perform ing trigger input multiple times as leads to malfunctioning Moreover whe...

Page 108: ...ETI instruction is executed unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state At initial reset this flag is set to 0 4 12 6 Programming notes 1 Perform data writing reading to the data registers SD0 SD7 only while the serial interface is not running i e the synchr...

Page 109: ...rammable dividing circuit 256 Hz One shot buzzer control circuit Duty ratio control circuit BZFQ0 BZFQ2 BDTY0 BDTY2 Buzzer output control circuit Envelope addition circuit ENON BZE ENRTM ENRST BZSTP BZSHT SHTPW BZ terminal Fig 4 13 1 1 Configuration of sound generator 4 13 2 Control of buzzer output The BZ and BZ signals generated by the sound generator are output from the BZ and BZ terminals by s...

Page 110: ...evel 7 Level 8 Min 4096 0 2048 0 8 16 7 16 6 16 5 16 4 16 3 16 2 16 1 16 3276 8 1638 4 8 20 7 20 6 20 5 20 4 20 3 20 2 20 1 20 2730 7 1365 3 12 24 11 24 10 24 9 24 8 24 7 24 6 24 5 24 2340 6 1170 3 12 28 11 28 10 28 9 28 8 28 7 28 6 28 5 28 Duty ratio by buzzer frequency Hz When the high level output time has been made TH and when the low level output time has been made TL due to the ratio of the ...

Page 111: ...uated down to level 8 minimum it is retained at that level The duty ratio can be returned to maximum by writing 1 into register ENRST during output of a envelope attached buzzer signal The envelope attenuation time time for changing of the duty ratio can be selected by the register ENRTM The time for a 1 stage level change is 62 5 msec 16 Hz when 0 has been written into ENRTM and 125 msec 8 Hz whe...

Page 112: ...so permits reading When BZSHT is 1 the one shot output circuit is in operation during one shot output and when it is 0 it shows that the circuit is in the ready outputtable status In addition it can also terminate one shot output prior to the elapsing of the set time This is done by writing a 1 into the one shot buzzer stop BZSTP In this case as well the buzzer signal goes off in synchronization w...

Page 113: ...BZSHT SHTPW 2 0 0 0 Stop Trigger Busy 125 msec Invalid Invalid Ready 31 25 msec Unused 1 shot buzzer stop writing 1 shot buzzer trigger writing 1 shot buzzer status reading 1 shot buzzer pulse width setting 1 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read BZE Buzzer output control register FF6CH D0 Controls the buzzer signal output When 1 is written Buzzer o...

Page 114: ... No operation Reading Always 0 Writing 1 into ENRST resets envelope and the duty ratio becomes maximum If an envelope has not been added ENON 0 and if no buzzer signal is being output the reset becomes invalid Writing 0 is also invalid This bit is dedicated for writing and is always 0 for reading ENON Envelope On Off control register FF6CH D1 Controls the addition of an envelope onto the buzzer si...

Page 115: ... When a re trigger is assigned during a one shot output the one shot output time set with SHTPW is measured again from that point time extension When reading When 1 is read BUSY When 0 is read READY During reading BZSHT shows the operation status of the one shot output circuit During one shot output BZSHT becomes 1 and the output goes off it shifts to 0 At initial reset this bit is set to 0 BZSTP ...

Page 116: ...rm a multiplication set the multiplier to the source register SR and the multiplicand to the low order 8 bits DRL of the destination register then write 0 to the calculation mode selection register CALMD The multiplication takes 10 CPU clock cycles from writing 0 to CALMD until the 16 bit product is loaded into the destination register DRH and DRL At the same time the result is loaded the operatio...

Page 117: ...ge Z flag Set when the 8 bit value in DRL is 00H and reset when it is not 00H Examples of division DRH DRL dividend SR divisor DRL quotient DRH remainder NF VF ZF 1A16H 64H 42H 4EH 0 0 0 332CH 64H 83H 00H 1 0 0 0000H 58H 00H 00H 0 0 1 2468H 13H 68H 24H 1 1 0 In the example of 2468H 13H shown above DRH DRL maintains the dividend because the quotient overflows the 8 bit To get the correct results wh...

Page 118: ...shows a sample program ldb ext src_data h ldb xl src_data l Set RAM address for operand ldb ext au h ldb yl au l Set multiplier I O memory address ldb ba x ldb y ba Set data to SR ldb ba x ldb y ba Set data to DRL ldb ba x ldb y ba Set data to DRH ld y 0b0001 Start operation select calculation mode ldb ext rslt_data h ldb xl rslt_data l Set result store address nop nop nop Dummy instructions to wa...

Page 119: ... DRH4 2 2 2 2 MSB High order 8 bit destination register high order 4 bits R W FF85H DRH7 DRH6 DRH5 DRH4 1 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read SR0 SR7 Source register FF80H FF81H Used to set multipliers and divisors Set the low order 4 bits of data to SR0 SR3 and the high order 4 bits to SR4 SR7 This register maintains the latest set value until th...

Page 120: ...al reset this flag is set to 0 VF Overflow flag FF86H D2 Indicates whether an overflow has occurred or not in a division process When 1 is read Overflow occurred When 0 is read Overflow has not occurred Writing Invalid When a multiplication process has finished this flag is always set to 0 VF is a read only bit so writing operation is invalid At initial reset this flag is set to 0 ZF Zero flag FF8...

Page 121: ...s can be connected The configuration of the R f converter is shown in Figure 4 15 1 1 REF VDD VSS SEN0 SEN1 RFIN Interrupt request CR oscillation control circuit Measurement counter Time base counter Data bus Interrupt control circuit OVTBC OVMC MC00 MC03 MC04 MC07 MC08 MC11 OSC1 oscillation circuit fOSC1 RFRUNS RFRUNR MC12 MC15 Time base counter control circuit TC00 TC03 TC04 TC07 TC08 TC11 TC12 ...

Page 122: ... VSS Tr1 SEN0 CR oscillation control circuit VDD RFIN Tr2 To measurement counter CRF RSEN0 Fig 4 15 2 2 CR oscillation circuit The Tr1 turns on first and the capacitor CRF connected between the VSS and RFIN terminals is charged through the sensor RSEN0 If the voltage level of the RFIN terminal increases the Tr1 turns off and the Tr2 turns on As a result the capacitor becomes discharged and oscilla...

Page 123: ...r after the R f conversion In other words the difference between the reference resistance and sensor oscillation frequencies can be found easily For instance if resistance values of the reference resistance and the sensor are equivalent the same value as the initial value before converting into a complement will be obtained as the result The time base counter allows reading of the counter value an...

Page 124: ...verting the sensor resistance independently the mea surement counter must be set to 00000H and the time base counter must be set to the value measured at the time of a reference oscillation When R f conversion is initiated by the RFRUNS register oscillation by the sensor begins and the measurement counter starts counting up from 00000H by the oscillation clock The time base counter also starts cou...

Page 125: ...unter overflows These flags are reset to 0 when R f conversion is started or when 1 is written to the flag When the interrupt occurs be sure to read the overflow flags and check overflow The initial value to be set depends on the measurable range by the sensor or where to set the reference resistance value within that range The initial value must be set taking the above into consideration Convert ...

Page 126: ...RFM and EIRFB When the EIRFM EIRFB has been set at 1 an interrupt occurs in the CPU When the EIRFM EIRFB is set at 0 no interrupt will occur in the CPU even if the interrupt factor flag is set to 1 The interrupt factor flag is reset to 0 by writing 1 Timing of interrupt by the R f converter is shown in Figures 4 15 4 1 to 4 15 4 4 n 0 FFFFCH FFFFBH n 1 n 2 n 3 FFFFD FFFFEH FFFFFH 0 x 3 x 2 x 1 x F...

Page 127: ...asurement counter OVTBC IRFB Interrupt request Count down Fig 4 15 4 4 Time base counter overflow interrupt Note When the R f converter interrupt is generated be sure to check whether or not the R f conversion has completed normally by reading the overflow flags When an interrupt occurs by the counter overflow the same interrupt will occur if the overflow flag OVMC or OVTBC is not reset Be sure to...

Page 128: ... TC11 TC10 TC9 TC8 2 2 2 2 Time base counter TC8 TC11 R W FF99H TC11 TC10 TC9 TC8 TC15 TC14 TC13 TC12 2 2 2 2 Time base counter TC12 TC15 R W FF9AH TC15 TC14 TC13 TC12 TC19 TC18 TC17 TC16 2 2 2 2 MSB Time base counter TC16 TC19 R W FF9BH TC19 TC18 TC17 TC16 TC3 TC2 TC1 TC0 2 2 2 2 Time base counter TC0 TC3 LSB R W FF97H TC3 TC2 TC1 TC0 TC7 TC6 TC5 TC4 2 2 2 2 Time base counter TC4 TC7 R W FF98H TC...

Page 129: ...d to adjust the CR oscillation time between the reference resistance and the sensor The time base counter counts down during oscillation of the reference resistance and counts up to 00000H during oscillation of the sensor 00000H needs to be entered in the counter prior to a reference oscillation in order to adjust the CR oscillating time number of clocks of both counts The counter value after a re...

Page 130: ...llation of the sensor OVMC is set to 1 and the interrupt occurs at the same time This flag is reset by writing 1 or starting R f conversion At initial reset this flag is set to 0 OVTBC Time base counter overflow flag FF91H D3 Indicates whether the time base counter has overflown When 1 is read Overflow has occurred When 0 is read Overflow has not occurred When 1 is written Flag reset When 0 is wri...

Page 131: ... 15 6 Programming notes 1 Depending on the initial value of the measurement counter MC the measurement counter or the time base counter may overflow while the CR oscillation clock is being counted When setting the initial value pay attention to CR oscillation frequency its fluctuation range and the input clock frequency of the time base counter If an overflow occurs R f conversion is terminated im...

Page 132: ... goes on and starts comparing the external voltages input to the two differential input terminals CMPP0 and CMPM0 The result can be read from the comparator comparison result detection bit CMPDT through the latch and when CMPP0 CMPM0 it is 1 and when CMPP0 CMPM0 it is 0 After the analog comparator is turned on a maximum of 3 msec is necessary until the output stabilizes Consequently allow an adequ...

Page 133: ...goes on by writing 1 to CMPON and goes off when 0 is written At initial reset this register is set 0 CMPDT analog comparator data FF05H D2 The comparison result of the analog comparator can be read out When 1 is read CMPP0 CMPM0 When 0 is read CMPP0 CMPM0 Writing Invalid The result of analog comparator can be read from CMPDT When the status of external voltage input to differential input terminals...

Page 134: ...urning the SVD circuit on off and the SVD criteria voltage setting can be done with software Figure 4 17 1 1 shows the configuration of the SVD circuit V Detection output Data bus DD VSS SVDON SVDS2 SVDS0 Criteria voltage setting circuit SVD circuit SVDDT SVD terminal Fig 4 17 1 1 Configuration of SVD circuit 4 17 2 Mask option Besides the supply voltage VDD terminal VSS terminal drop detection th...

Page 135: ... 0 is written to the SVDS2 SVDS0 register the supply voltage detection voltage is set to 1 85 V However when External voltage detection is selected by mask option the SVD circuit does not compare the supply voltage VDD terminal VSS terminal but compares between the external voltage SVD termi nal VSS terminal input from the SVD terminal and 0 98 V When the SVDON register is set to 1 source voltage ...

Page 136: ...VD control on off register FF05H D0 Turns the SVD circuit on and off When 1 is written SVD circuit ON When 0 is written SVD circuit OFF Reading Valid When SVDON is set to 1 a source voltage detection is executed by the SVD circuit As soon as SVDON is reset to 0 the result is loaded to the SVDDT latch To obtain a stable detection result the SVD circuit must be on for at least 500 µsec At initial re...

Page 137: ...he interrupt flag setting Also the interrupt mask register is not provided However it is possible to not generate NMI since software can stop the watchdog timer operation Figure 4 18 1 shows the configuration of the interrupt circuit Note After an initial reset all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set with the software Be sure to set the SP1 and...

Page 138: ...T2 IT1 EIT1 IT0 EIT0 IRUN EIRUN ILAP EILAP ISW1 EISW1 ISW10 EISW10 IRFM EIRFM IRFB EIRFB IPT1 EIPT1 IPT2 EIPT2 IPT0 EIPT0 Interrupt vector generation circuit Program counter low order 4 bits INT Interrupt request Interrupt factor flag Interrupt mask register Input comparison register Interrupt selection register Interrupt flag ISIF EISIF K00 KCP00 SIK00 K01 KCP01 SIK01 K02 KCP02 SIK02 K03 KCP03 SI...

Page 139: ...ogrammable timer 0 counter 0 Serial interface 8 bit data input output completion K00 K03 input falling edge or rising edge K10 K13 input falling edge or rising edge Clock timer 1 Hz falling edge Clock timer 2 Hz falling edge Clock timer 8 Hz falling edge Clock timer 32 Hz falling edge Stopwatch timer Direct RUN Stopwatch timer Direct LAP Stopwatch timer 1 Hz Stopwatch timer 10 Hz R f converter end...

Page 140: ...H D0 FFE5H D3 FFE5H D2 FFE5H D1 FFE5H D0 FFE6H D3 FFE6H D2 FFE6H D1 FFE6H D0 FFE7H D1 FFE7H D0 Interrupt mask register 4 18 3 Interrupt vector When an interrupt request is input to the CPU the CPU begins interrupt processing After the program being executed is terminated the interrupt processing is executed in the following order 1 The content of the flag register is evacuated then the I flag is r...

Page 141: ... 3 EIK0 2 2 2 0 Enable Mask Unused Unused Unused Interrupt mask register K00 K03 FFE5H EIT3 EIT2 EIT1 EIT0 R W EIT3 EIT2 EIT1 EIT0 0 0 0 0 Enable Enable Enable Enable Mask Mask Mask Mask Interrupt mask register Clock timer 1 Hz Interrupt mask register Clock timer 2 Hz Interrupt mask register Clock timer 8 Hz Interrupt mask register Clock timer 32 Hz FFE4H 0 0 0 EIK1 R R W 0 3 0 3 0 3 EIK1 2 2 2 0 ...

Page 142: ...Invalid Unused Unused Unused Interrupt factor flag K00 K03 FFF4H 0 0 0 IK1 R R W 0 3 0 3 0 3 IK1 2 2 2 0 R Yes W Reset R No W Invalid Unused Unused Unused Interrupt factor flag K10 K13 1 Initial value at initial reset 2 Not set in the circuit 3 Constantly 0 when being read EIPT2 EIPT1 EIPT0 Interrupt mask registers FFE1H D2 D1 D0 IPT2 IPT1 IPT0 Interrupt factor flags FFF1H D2 D1 D0 Refer to Sectio...

Page 143: ...xecuted unless the interrupt factor flag is reset Therefore be sure to reset write 1 to the interrupt factor flag in the interrupt service routine before shifting to the interrupt enabled state 3 After an initial reset all the interrupts including NMI are masked until both the stack pointers SP1 and SP2 are set with the software Be sure to set the SP1 and SP2 in the initialize routine Further when...

Page 144: ...LCD system voltage circuit Voltage halver mode SVD circuit Analog comparator Control register HALT instruction CLKCHG OSCC VDC0 VDC1 LPWR VDC2 VDC3 SVDON CMPON Refer to Chapter 7 Electrical Characteristics for current consumption Below are the circuit statuses at initial reset CPU Operating status CPU operating frequency Low speed side CLKCHG 0 OSC3 oscillation circuit is in off status OSCC 0 Inte...

Page 145: ...e that the supply voltage is 2 4 V or higher using the SVD circuit before writing 1 to VDC2 Furthermore switch the CPU clock to OSC1 2 When setting the LCD system voltage circuit into the halver mode make sure that the supply voltage is 2 4 V or higher using the SVD circuit before writing 1 to VDC3 Furthermore set the VC1 voltage contrast to 1 13 V or lower LC register 6 or less Watchdog timer 1 W...

Page 146: ...ci tance Hence when fetching input ports set an appropriate wait time Particular care needs to be taken of the key scan during key matrix configuration Make this waiting time the amount of time or more calculated by the following expression 10 C R C terminal capacitance 5 pF parasitic capacitance pF R pull down resistance 375 kΩ Max LCD driver Because at initial reset the contents of display memor...

Page 147: ...s Then it starts loading the reload data to the counter and the counter data is determined at the next rising edge of the input clock period shown in as in the figure Input clock Counter data continuous mode Reload data 25H 03H 02H 01H 00H 25H 24H Counter data is determined by reloading Underflow interrupt is generated Fig 5 2 2 Reload timing for programmable timer To avoid improper reloading do n...

Page 148: ...e measurement counter always write 5 words of data continuously in order from the lower address FF92H FF93H FF94H FF95H FF96H Furthermore an LD instruction should be used for writing data to the measurement counter and a read modify write instruction AND OR ADD SUB etc cannot be used Analog comparator 1 To reduce current consumption turn the analog comparator off CMPON 0 when it is not neces sary ...

Page 149: ... on reset signal which is input to the RESET terminal changes depending on conditions power rise time components used board pattern etc Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product When using the built in pull down resistor of the RESET terminal take into consideration dispersion of the resistance for setting the constan...

Page 150: ...may cause a malfunction Do not arrange a high speed signal line especially near circuits that are sensitive to noise such as the oscillation unit and analog input unit OSC4 OSC3 VSS Large current signal line High speed signal line Prohibited pattern example Precautions for Visible Radiation when bare chip is mounted Visible radiation causes semiconductor devices to change the electrical characteri...

Page 151: ...tion 2 CR oscillation external R CGC V C1 V C2 V C3 Piezo RA1 RA2 Input I O Output S1C63666 The potential of the substrate back of the chip is VSS RFOUT SEN0 SEN1 REF RFIN C AD R REF Sensor0 Sensor1 BZ BZ CMPP0 CMPM0 X tal CGX CR CGC CDC RCR C1 C8 CP CRES RA1 RA2 Crystal oscillator Trimmer capacitor Ceramic oscillator Gate capacitor Drain capacitor Resistor for OSC3 CR oscillation Capacitor Capaci...

Page 152: ...el input current 1 High level input current 2 High level input current 3 Low level input current 1 Low level input current 2 Low level input current 3 High level output current 1 High level output current 2 Low level output current 1 Low level output current 2 Common output current Segment output current during LCD output Segment output current during DC output R f converter transistor ON resistan...

Page 153: ...µA µA µA µA µA µA µA µA µA Typ 100mV 1 08 500 1 80 0 90 2 8 1 4 5 0 3 5 800 1000 600 10 10 4 150 1 85 2 00 2 15 2 30 2 45 2 60 2 75 2 90 0 98 0 90 0 45 1 4 0 65 4 0 2 5 400 800 350 5 5 2 100 Typ 100mV 0 88 No panel load When SVD circuit R f converter and analog comparator are in OFF status VDC0 VDC1 0 OSCC 0 VDC2 VDC3 0 VDC2 VDC3 1 VDC0 VDC1 1 OSCC 1 VDC2 VDC3 0 Do not input a voltage exceeding th...

Page 154: ... 3 0V VSS 0V fOSC1 32 768kHz CG 25pF CD built in Ta 20 to 70 C OSC3 ceramic oscillation circuit Item Oscillation start voltage Oscillation start time Oscillation stop voltage Symbol Vsta tsta Vstp Unit V ms V Max 5 Typ Min 2 4 2 4 Condition VDD VDD 2 4 to 3 6V VDD Unless otherwise specified VDD 3 0V VSS 0V Ceramic oscillator 4MHz CGC CDC 30pF Ta 20 to 70 C OSC3 CR oscillation circuit built in R ty...

Page 155: ...oscillation characteristics change depending on the conditions components used board pattern etc Use the following characteristics as reference values and evaluate the characteristics on the actual product Resistor value for CR oscillation RCR kΩ CR oscillation frequency f OSC3 kHz 0 20 40 60 80 100 120 10000 1000 100 VDD 2 4 3 6 V Ta 25 C Typ value ...

Page 156: ... 1 MHz Condition VDD 3 0V VSS 0V Ta 25 C VIH1 0 8VDD VIL1 0 2VDD VOH 0 8VDD VOL 0 2VDD Clock synchronous slave mode During 32 kHz operation Item Transmitting data output delay time Receiving data input set up time Receiving data input hold time Symbol tssd tsss tssh Unit µs µs µs Max 10 Typ Min 10 5 Condition VDD 3 0V VSS 0V Ta 25 C VIH1 0 8VDD VIL1 0 2VDD VOH 0 8VDD VOL 0 2VDD During 4 MHz operat...

Page 157: ... converter oscillation frequency capacitance characteristic Capacitance pF external RFIN Oscillation frequency Hz 470 1 000 2 200 4 700 Typ 1 000 000 100 000 10 000 1 000 100 10 1 Ta 20 70 C R 50 kΩ VDD 3 0 V 20 20 R f converter oscillation frequency resistance characteristic Resistance kΩ external SEN0 SEN1 or REF Oscillation frequency Hz 1 Typ 10 100 1 000 1 000 000 100 000 10 000 1 000 100 10 1...

Page 158: ...PACKAGE CHAPTER 8 PACKAGE 8 1 Plastic Package QFP20 144pin Unit mm The dimensions are subject to change without notice 20 0 1 22 0 4 73 108 20 0 1 22 0 4 37 72 INDEX 0 2 36 1 144 109 1 4 0 1 0 1 1 7 max 1 0 5 0 2 0 10 0 125 0 5 0 1 0 05 0 05 0 025 ...

Page 159: ...6 TECHNICAL MANUAL EPSON 149 CHAPTER 8 PACKAGE 8 2 Ceramic Package for Test Samples QFP17 144pin Unit mm 19 20 0 19 22 00 0 25 19 20 0 19 22 00 0 25 0 20 0 50 2 80 Max 0 50 0 20 0 15 73 108 37 72 36 1 144 109 ...

Page 160: ...NUAL CHAPTER 9 PAD LAYOUT CHAPTER 9 PAD LAYOUT 9 1 Diagram of Pad Layout Chip thickness 400 µm Pad opening 85 µm X Y 0 0 4 75 mm 4 95 mm 1 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135 Die No ...

Page 161: ... K10 K11 K12 K13 P00 P01 P02 P03 P10 P11 P12 P13 R00 X 2 241 2 241 2 241 2 241 2 241 2 241 2 241 2 241 2 241 2 241 2 241 2 241 2 241 2 241 2 241 2 241 2 241 2 241 2 241 2 241 2 241 2 241 2 241 1 982 1 867 1 751 1 636 1 520 1 405 1 289 1 174 1 058 943 827 712 596 481 365 250 134 19 97 212 328 443 Y 580 460 340 220 100 20 140 260 380 500 620 740 860 980 1 100 1 220 1 340 1 460 1 580 1 754 1 925 2 09...

Page 162: ...anual provided with your ICE for detailed information on its functions and method of use A 1 Names and Functions of Each Part The following explains the names and functions of each part of the board S5U1C63000P1 V S V D F P G A Prog PRG Norm 1 1 2 15 LED VC5 V L C D P R C 6 3 0 0 0 Ver x x VC5 CLK CN0 GND GND FOSC3 CR FOSC1 CR ADOSCA SN0 ST1 ST0 LCLK 32K EPROM CONFIG SEL Flash CPA1 E IOSEL2 OSC1 C...

Page 163: ...8 10 12 14 16 LED 5 CR oscillation frequency adjusting control When OSC3 is set for a CR oscillation circuit by mask option this control allows you to adjust the oscillation frequency The oscillation frequency can be adjusted in the range of approx 100 kHz to 8 MHz Note that the actual IC does not operate with all of these frequencies consult the technical manual for the S1C63666 to select the app...

Page 164: ...may not be able to start when you power on the ICE once again In this case temporarily power off the ICE and set CLK to the 32K position and the PRG switch to the Prog position then switch on power for the ICE once again This should allow the debugger to start up allowing you to download circuit data After downloading the circuit data temporarily power off the ICE and reset CLK and PRG to the LCLK...

Page 165: ...arget system To connect this board S5U1C63000P1 to the target system use the I O connecting cables supplied with the board 80 pin 40 pin 2 100 pin 50 pin 2 flat type Take care when handling the connectors since they conduct electrical power VDD 3 3 V CN1 1 40 pin CN1 2 40 pin I O connection cable To target board mark CN2 1 50 pin CN2 2 50 pin Fig A 2 1 Connecting the S5U1C63000P1 to the target sys...

Page 166: ...ESET VSS VSS No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 50 pin CN2 1 connector Pin name VDD 3 3 V VDD 3 3 V SEG0 DC SEG1 DC SEG2 DC SEG3 DC SEG4 DC SEG5 DC SEG6 DC SEG7 DC VSS VSS SEG8 DC SEG9 DC SEG10 DC SEG11 DC SEG12 DC SEG13 DC SEG14 DC SEG15 DC VDD 3 3 V VDD 3 3 V SEG16 DC SEG17 DC SEG18 DC SE...

Page 167: ...ing the output ports for open drain mode Pull down resistance value The pull down resistance values on this board are set to 220 kΩ which differ from those for the actual IC For the resistance values on the actual IC refer to the technical manual for the S1C63666 Note that when using pull down resistors to pull the input pins low the input pins may require a certain period to reach a valid low lev...

Page 168: ... Use separate instructions to switch the clock from OSC3 to OSC1 and to turn off the OSC3 oscillation circuit If executed simultaneously with a single instruction these operations although good with this board may not function properly well with the actual IC Because the logic level of the oscillation circuit is high the timing at which the oscillation starts on this board differs from that of the...

Page 169: ...al to determine the appropriate wait time to be inserted The LCD drive voltage on this board is different from that on the actual IC Since the usable operating frequency range depends on the device s internal operating voltage consult the technical manual for the S1C63666 to ensure that the device will not be operated with an inappropriate combination of the operating frequency and the internal po...

Page 170: ...rth RD DongSanHuan ChaoYang District Beijing CHINA Phone 86 10 6410 6655 Fax 86 10 6410 7320 SHANGHAI BRANCH 7F High Tech Bldg 900 Yishan Road Shanghai 200233 CHINA Phone 86 21 5423 5522 Fax 86 21 5423 5512 EPSON HONG KONG LTD 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Phone 852 2585 4600 Fax 852 2827 4346 Telex 65542 EPSCO HX EPSON Electronic Technology Development Shenzhen LTD 12 F Da...

Page 171: ...ical Manual S1C63666 First issue November 2001 Printed March 2007 in Japan A L M EPSON Electronic Devices Website SEMICONDUCTOR OPERATIONS DIVISION http www epson jp device semicon_e Document code 404519503 ...

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