III PERIPHERAL BLOCK: SERIAL INTERFACE
S1C33210 FUNCTION PART
EPSON
B-III-8-13
Setting Asynchronous Interface
When performing asynchronous transfer via the serial interface, the following must be done before data transfer can
be started:
1. Setting input/output pins
2. Setting the interface mode
3. Setting the transfer mode
4. Setting the input clock
5. Setting the data format
6. Setting interrupt/IDMA/HSDMA
The following describes how to set each of the above. For details on interrupt/DMA settings, refer to "Serial
Interface Interrupts and DMA".
Note: Always make sure the serial interface is inactive (TXENx and RXENx = "0") before making these
settings. A change in settings during operation may result in a malfunction.
Setting input/output pins
In the asynchronous mode, two pins–SINx and SOUTx–are used. When external clock input is used for Ch. 0
and Ch. 2, one more pin, #SCLKx, is also used.
Set CFP0[7:0] (D[7:0]) / P0 function select register (0x402D0) according to the pins used. (Both channels can
be used, if necessary.) Since the #SRDYx pin is not used, P03 or P24 can be used as an I/O port. During
operation using the internal clock, P02 or P25 can also be used as an I/O port.
Setting the interface mode
IRMDx[1:0] (D[1:0]) / Serial I/F IrDA register (Ch.0: 0x401E4, Ch.1: 0x401E9, Ch.2: 0x401F4, Ch.3:
0x401F9) is used to set the IrDA interface. Since IRMDx[1:0] becomes indeterminate at initial reset, initialize
it by writing "00" when using the serial interface as a normal interface, or "10" when using the serial interface as
an IrDA interface. This setting must be made before a transfer mode is set.
Setting the transfer mode
Use SMDx to set the transfer mode of the serial interface as described earlier. When using the serial interface in
the 8-bit asynchronous mode, set SMDx[1:0] to "11", when using the serial interface in the 7-bit asynchronous
mode, set SMDx[1:0] to "10".
Setting the input clock
In the asynchronous mode, the operating clock can be selected between the internal clock and an external clock.
Ch.0 input clock selection: SSCK0 (D2) / Serial I/F Ch.0 control register (0x401E3)
Ch.1 input clock selection: SSCK1 (D2) / Serial I/F Ch.1 control register (0x401E8)
Ch.2 input clock selection: SSCK2 (D2) / Serial I/F Ch.2 control register (0x401F3)
Ch.3 input clock selection: SSCK3 (D2) / Serial I/F Ch.3 control register (0x401F8)
The external clock is selected (input from the #SCLKx pin) by writing "1" to SSCKx, and an internal clock is
selected by writing "0".
Note: SSCKx becomes indeterminate at initial reset, so be sure to reset it in the software.
SSCK11 and SSCK31 must be "0" because Ch. 1 and Ch. 3 support only asynchronous operation.
• Internal clock
When the internal clock is selected, the serial interface is clocked by a clock generated using an 8-bit
programmable timer. The clock source for each channel is as follows:
Ch.0: Clock output by 8-bit programmable timer 2
Ch.1: Clock output by 8-bit programmable timer 3
Ch.2: Clock output by 8-bit programmable timer 4
Ch.3: Clock output by 8-bit programmable timer 5
Therefore, before the internal clock can be used, the following conditions must be met:
1. The prescaler is outputting a clock to the 8-bit programmable timer 2 (or 3).
2. The 8-bit programmable timer 2 (or 3) is outputting a clock.
Summary of Contents for S1C33210
Page 4: ......
Page 13: ...S1C33210 PRODUCT PART ...
Page 14: ......
Page 124: ...APPENDIX B PIN CHARACTERISTICS A 110 EPSON S1C33210 PRODUCT PART THIS PAGE IS BLANK ...
Page 125: ...S1C33210 FUNCTION PART ...
Page 126: ......
Page 127: ...S1C33210 FUNCTION PART I OUTLINE ...
Page 128: ......
Page 130: ...I OUTLINE INTRODUCTION B I 1 2 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK ...
Page 138: ...I OUTLINE LIST OF PINS B I 3 6 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK ...
Page 139: ...S1C33210 FUNCTION PART II CORE BLOCK ...
Page 140: ......
Page 142: ...II CORE BLOCK INTRODUCTION B II 1 2 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK ...
Page 148: ...II CORE BLOCK CPU AND OPERATING MODE B II 2 6 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK ...
Page 152: ...II CORE BLOCK INITIAL RESET B II 3 4 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK ...
Page 234: ...II CORE BLOCK CLG Clock Generator B II 6 10 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK ...
Page 236: ...II CORE BLOCK DBG Debug Unit B II 7 2 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK ...
Page 237: ...S1C33210 FUNCTION PART III PERIPHERAL BLOCK ...
Page 238: ......
Page 240: ...III PERIPHERAL BLOCK INTRODUCTION B III 1 2 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK ...
Page 296: ...III PERIPHERAL BLOCK WATCHDOG TIMER B III 5 4 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK ...
Page 429: ...S1C33210 FUNCTION PART IV ANALOG BLOCK ...
Page 430: ......
Page 432: ...IV ANALOG BLOCK INTRODUCTION B IV 1 2 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK ...
Page 448: ...IV ANALOG BLOCK A D CONVERTER B IV 2 16 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK ...
Page 449: ...S1C33210 FUNCTION PART V DMA BLOCK ...
Page 450: ......
Page 452: ...V DMA BLOCK INTRODUCTION B V 1 2 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK ...
Page 506: ...V DMA BLOCK IDMA Intelligent DMA B V 3 18 EPSON S1C33210 FUNCTION PART THIS PAGE IS BLANK ...
Page 507: ...S1C33210 FUNCTION PART Appendix I O MAP ...
Page 508: ......
Page 557: ......