18 uaRT
18-4
Seiko epson Corporation
S1C17624/604/622/602/621 TeChniCal Manual
The transmitter circuit includes two status flags: TDBE/UART_ST
x
register and TRBS/UART_ST
x
register.
The TDBE flag indicates the transmit data buffer status. This flag switches to 0 when the application program
writes data to the transmit data buffer and reverts to 1 when the buffer data is sent to the transmit shift register.
An interrupt can be generated when this flag is set to 1 (see Section 18.7). Subsequent data is sent after con-
firming that the transmit data buffer is empty either by using this interrupt or by reading the TDBE flag. The
transmit data buffer size is 1 byte, but a shift register is provided separately to allow data to be written while the
previous data is being sent. Always confirm that the transmit data buffer is empty before writing transmit data.
Writing data while the TDBE flag is 0 will overwrite earlier transmit data inside the transmit data buffer.
The TRBS flag indicates the shift register status. This flag switches to 1 when transmit data is loaded from the
transmit data buffer to the shift register and reverts to 0 once the data is sent. Read this flag to check whether
the transmitter circuit is operating or at standby.
S1: Start bit, S2: Stop bit, P: Parity bit, Wr: Data write to transmit data buffer
Sampling clock (sclk)
SOUT
x
TDBE
TRBS
Interrupt
S1 D0 D1 D2 D3 D4 D5 D6 D7 P S2 S1 D0 D1
D7 P S2 S1 D0 D1
D7 P
Wr
Wr
Wr
S2
Transmit buffer empty interrupt request
5.1 Data Transmission Timing Chart
Figure 18.
Data reception control
The receiver circuit is activated by setting RXEN to 1, enabling data to be received from an external serial de-
vice.
When the external serial device sends a start bit, the receiver circuit detects its Low level and starts sampling
the following data bits. The data bits are sampled at the sampling clock rising edge, and the lead bit is loaded
into the receive shift register as LSB. Once the MSB has been received into the shift register, the received data
is loaded into the receive data buffer. If parity checking is enabled, the receiver circuit checks the received data
at the same time by checking the parity bit received immediately after the MSB.
The receive data buffer, a 2-byte FIFO, receives data until full.
Received data in the buffer can be read from RXD[7:0]/UART_RXD
x
register. The oldest data is read out first
and data is cleared by reading.
The receiver circuit includes two buffer status flags: RDRY/UART_ST
x
register and RD2B/UART_ST
x
regis-
ter.
The RDRY flag indicates that the receive data buffer still contains data. The RD2B flag indicates that the re-
ceive data buffer is full.
(1) RDRY = 0, RD2B = 0
The receive data buffer contents need not be read, since no data has been received.
(2) RDRY = 1, RD2B = 0
One 8-bit data has been received. Read the receive data buffer contents once. This resets the RDRY flag.
The buffer reverts to state (1) above.
If the receive data buffer contents are read twice, the second data read will be invalid.
(3) RDRY = 1, RD2B = 1
Two 8-bit data have been received. Read the receive data buffer contents twice. The receive data buffer
outputs the oldest data first. This resets the RD2B flag. The buffer then reverts to the state in (2) above. The
second read outputs the most recent received data, after which the buffer reverts to the state in (1) above.
