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Epson S1C17602, Technical Manual

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3  MeMORY MaP

S1C17624/604/622/602/621 TeChniCal Manual

  Seiko epson Corporation 

3-3

Bus Cycle

3.1  

The CPU operates with CCLK as the operating clock. For CCLK, see “Controlling the CPU Core Clock (CCLK)” 
in the “Clock Generator (CLG)” chapter.
The period between a CCLK rising edge and the next rising edge is assumed to be one CCLK (= one bus cycle). As 
shown in Figures 3.1 to 3.3, the number of cycles required for one bus access depends on the peripheral or memory 
module. Furthermore, the number of bus accesses depends on the CPU instruction (access size) and device size.

1.1  Number of Bus Accesses

Table 3.

Device size

CPu access size

number of bus accesses

8 bits

  8 bits

1

16 bits

2

32 bits

*

4

16 bits

  8 bits

1

16 bits

1

32 bits

*

2

32 bits

  8 bits

1

16 bits

1

32 bits

*

1

*

 

Handling the eight high-order bits during 32-bit accesses

  During writing, the eight high-order bits are written as 0. During reading from a memory, the eight high-order 

bits are ignored. However, the stack operation in an interrupt handling reads/writes 32-bit data that consists of the 
PSR value as the high-order 8 bits and the return address as the low order 24 bits.

number of bus cycles calculation example 

 

Number of bus cycles when the CPU accesses the display RAM area (eight-bit device, set to two access cycles) 
by a 16-bit read or write instruction.

 

 

2 [cycles] 

×

 2 [bus accesses] = 4 [CCLK cycles]

Restrictions on access Size

3.1.1  

The modules shown below have a restriction on the access size. Appropriate instructions should be used in pro-
gramming.

Flash memory

 

The Flash memory allows only 16-bit write instructions for programming. Reading data from the Flash memory 
has no such restriction.

Other modules can be accessed with an 8-bit, 16-bit, or 32-bit instruction. However, reading for an unnecessary 
register may change the peripheral  module status and it may cause a problem. Therefore, use the appropriate in-
structions according to the device size.

Restrictions on instruction execution Cycles

3.1.2  

An instruction fetch and a data access are not performed simultaneously under one of the conditions listed below. 
This prolongs the instruction fetch cycle for the number of data area access cycles.

•  When the CPU executes the instruction stored in the Flash area and accesses data in the Flash area or display 

RAM area

•  When the CPU executes the instruction stored in the internal RAM area and accesses data in the internal RAM 

area

Summary of Contents for S1C17602

Page 1: ...Rev 1 3 CMOS 16 BiT SinGle ChiP MiCROCOnTROlleR S1C17624 604 622 602 621 Technical Manual ...

Page 2: ... any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party When exporting the products or technology described in this material you should comply with the applicable export control laws and regulations and follow the pr...

Page 3: ...ation Package D die form F QFP B BGA WCSP Model number Model name C microcomputer digital products Product classification S1 semiconductor Development tools S5U1 C 17000 H2 1 Packing specifications 00 standard packing Version 1 Version 1 Tool type Hx ICE Dx Evaluation board Ex ROM emulation board Mx Emulation memory for external ROM Tx A socket for mounting Cx Compiler package Sx Middleware packag...

Page 4: ...sh Programming 3 4 3 2 3 Protect Bits 3 4 3 2 4 Access Control for the Flash Controller 3 5 FLASHC Control Register MISC_FL 3 5 3 3 Internal RAM Area 3 6 3 3 1 Embedded RAM 3 6 IRAM Size Select Register MISC_IRAMSZ 3 6 3 4 Display RAM Area 3 7 3 5 Internal Peripheral Area 3 7 3 5 1 Internal Peripheral Area 1 0x4000 3 7 3 5 2 Internal Peripheral Area 2 0x5000 3 8 3 6 S1C17 Core I O Area 3 8 4 Power...

Page 5: ...CPU Core Clock CCLK Control 7 7 7 6 Peripheral Module Clock PCLK Control 7 7 7 7 Clock External Output FOUTH FOUT1 7 9 7 8 RESET and NMI Input Noise Filters 7 10 7 9 Control Register Details 7 10 Prescaler Control Register PSC_CTL 7 10 Clock Source Select Register OSC_SRC 7 10 Oscillation Control Register OSC_CTL 7 11 Noise Filter Enable Register OSC_NFEN 7 13 FOUT Control Register OSC_FOUT 7 13 P...

Page 6: ...rupt Flag Registers Px_IFLG 9 10 Px Port Chattering Filter Control Registers Px_CHAT 9 11 P0 Port Key Entry Reset Configuration Register P0_KRST 9 12 Px Port Input Enable Registers Px_IEN 9 12 P0 3 0 Port Function Select Register P00_03PMUX 9 13 P0 7 4 Port Function Select Register P04_07PMUX 9 14 P1 3 0 Port Function Select Register P10_13PMUX 9 15 P1 7 4 Port Function Select Register P14_17PMUX ...

Page 7: ...rs T16_INTx 11 10 12 16 bit PWM Timer T16e 12 1 12 1 T16E Module Overview 12 1 12 2 T16E Input Output Pins 12 2 12 3 Operating Modes 12 2 12 3 1 Internal Clock Mode 12 2 12 3 2 External Clock Mode 12 2 12 4 Setting and Resetting Counter Value 12 3 12 5 Compare Data Settings 12 3 12 6 Timer RUN STOP Control 12 3 12 7 Clock Output Control 12 4 12 8 T16E Interrupts 12 6 12 9 Control Register Details ...

Page 8: ...1 14 2 T8OSC1 Output Pin 14 1 14 3 Count Clock 14 2 14 4 Count Mode 14 2 14 5 Counter Reset 14 3 14 6 Compare Data Settings 14 3 14 7 Timer RUN STOP Control 14 3 14 8 PWM Output 14 4 14 9 T8OSC1 Interrupts 14 5 14 10 Control Register Details 14 5 T8OSC1 Clock Control Register OSC_T8OSC1 14 5 T8OSC1 Control Register T8OSC1_CTL 14 6 T8OSC1 Counter Data Register T8OSC1_CNT 14 7 T8OSC1 Compare Data Re...

Page 9: ...18 2 18 4 Transfer Data Settings 18 2 18 5 Data Transfer Control 18 3 18 6 Receive Errors 18 5 18 7 UART Interrupts 18 6 18 8 IrDA Interface 18 7 18 9 Control Register Details 18 8 UART Ch x Status Registers UART_STx 18 8 UART Ch x Transmit Data Registers UART_TXDx 18 10 UART Ch x Receive Data Registers UART_RXDx 18 10 UART Ch x Mode Registers UART_MODx 18 10 UART Ch x Control Registers UART_CTLx ...

Page 10: ... Control Register I2CS_CTL 21 11 I2C Slave Status Register I2CS_STAT 21 13 I2C Slave Access Status Register I2CS_ASTAT 21 15 I2C Slave Interrupt Control Register I2CS_ICTL 21 16 22 iR Remote Controller ReMC 22 1 22 1 REMC Module Overview 22 1 22 2 REMC Input Output Pins 22 1 22 3 Carrier Generation 22 1 22 4 Data Length Counter Clock Settings 22 2 22 5 Data Transfer Control 22 3 22 6 REMC Interrup...

Page 11: ...version 24 5 24 4 3 Reading A D Conversion Results 24 6 24 4 4 Terminating A D Conversion 24 6 24 4 5 Timing Charts 24 6 24 5 A D Converter Interrupts 24 7 24 6 Control Register Details 24 8 A D Conversion Result Register ADC10_ADD 24 8 A D Trigger Channel Select Register ADC10_TRG 24 9 A D Control Status Register ADC10_CTL 24 10 A D Clock Control Register ADC_DIV 24 12 25 R F Converter RFC 25 1 2...

Page 12: ...tails 27 2 Prescaler Control Register PSC_CTL 27 2 OSC1 Peripheral Control Register MISC_OSC1 27 3 IRAM Size Select Register MISC_IRAMSZ 27 3 Debug RAM Base Register DBRAM 27 4 Debug Control Register DCR 27 5 Instruction Break Address Register 2 IBAR2 27 6 Instruction Break Address Register 3 IBAR3 27 6 Instruction Break Address Register 4 IBAR4 27 6 28 Multiplier Divider COPRO 28 1 28 1 Overview ...

Page 13: ... A 13 0x5065 0x50c0 0x50c5 8 bit OSC1 Timer AP A 13 0x5066 0x5100 0x5104 SVD Circuit AP A 14 0x5120 Power Generator AP A 14 0x506e 0x5140 0x514a Real time Clock S1C17624 604 AP A 14 0x5200 0x52ab P Port Port MUX AP A 15 0x5300 0x530c 16 bit PWM Timer T16E Ch 0 AP A 22 0x4020 0x5320 0x532c MISC Registers AP A 22 0x5340 0x5346 IR Remote Controller AP A 24 0x5380 0x5386 A D Converter AP A 24 0x5067 0...

Page 14: ...lay Features 1 1 The main features of the S1C17624 604 622 602 621 are listed below 1 1 Features Table 1 Model S1C17624 S1C17604 S1C17622 S1C17602 S1C17621 CPu CPU core Seiko Epson original 16 bit RISC CPU core S1C17 Multiplier Divider COPRO 16 bit 16 bit multiplier 16 bit 16 bit 32 bit multiply and accumulation unit 16 bit 16 bit divider embedded Flash memory Capacity 128K bytes 64K bytes 32K byt...

Page 15: ...nterrupt RESET pin NMI Watchdog timer Programmable interrupts 20 systems 8 levels 19 systems 8 levels Power supply voltage Operating voltage VDD 1 8 V to 3 6 V for normal operation 2 7 V to 3 6 V for Flash erasing programming Built in voltage regulator two operating voltages switchable Analog voltage AVDD AVDD VDD Operating temperature Operating temperature range 25 C to 70 C Current consumption T...

Page 16: ...X EXCL0 2 Real time clock RTC 2 R F converter RFC a D converter aDC10 i2C slave i2CS SDA1 SCL1 BFR 8 bit timer T8F Test circuit 16 bit PWM timer T16e EXCL3 TOUT3 TOUTN3 RFIN0 1 REF0 1 SENA0 1 SENB0 1 RFCLKO AVDD AIN0 AIN7 ADTRG 8 bit OSC1 timer T8OSC1 TOUT4 2 1 Block Diagram Figure 1 1 The models have a different memory size LCD outputs and I O port configurations 2 The real time clock RTC and 16 ...

Page 17: ...G P02 eXCl0 P01 REMI P00 REMO ReSeT TeST OSC1 OSC2 V D1 V SS OSC3 OSC4 V DD 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 VSS VC1 VC2 VC3 Ca CB N C N C COM0 COM1 COM2 COM3 SeG55 COM4 SeG54 COM5 SeG53 COM6 SeG52 COM7 SeG51 SeG...

Page 18: ...7 SeG36 SCLK1 AIN4 P16 AIN3 P17 AIN2 P20 AIN1 P21 AIN0 P22 VDD SENB0 P23 SENA0 P24 REF0 P25 RFIN0 P26 VSS SOUT1 RFIN1 P27 SIN1 REF1 P30 SCL0 SENA1 TOUTA5 CAPA5 P31 SDA0 SENB1 TOUTB5 CAPB5 P32 BFR P53 LFRO P54 TOUTA6 CAPA6 P55 TOUTB6 CAPB6 P56 SCL1 SCL0 TOUTA6 CAPA6 P33 SDA1 SDA0 TOUTB6 CAPB6 P34 FOUT1 BFR P35 TOUT3 RFCLKO eXCl5 P36 TOUTN3 LFRO TOUT4 eXCl6 P37 FOUTH P40 P41 DSiO P42 DST2 P43 DClK N...

Page 19: ... 2 027 31 SEG34 1 450 2 027 96 VSS 1 450 2 027 32 SEG35 1 550 2 027 97 AVDD 1 550 2 027 33 SEG36 1 999 1 530 98 P16 SCLK1 AIN4 1 999 1 570 34 SEG37 1 999 1 430 99 P17 AIN3 1 999 1 470 35 SEG38 1 999 1 330 100 P20 AIN2 1 999 1 370 36 SEG39 1 999 1 230 101 P21 AIN1 1 999 1 270 37 SEG40 1 999 1 130 102 P22 AIN0 1 999 1 170 38 SEG41 1 999 1 030 103 VDD 1 999 1 070 39 SEG42 1 999 0 930 104 P23 SENB0 1 ...

Page 20: ...REMI P00 REMO ReSeT TeST OSC1 OSC2 V D1 V SS OSC3 OSC4 V DD 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VSS VC1 VC2 VC3 Ca CB N C COM0 COM1 COM2 COM3 SeG39 COM4 SeG38 COM5 SeG37 COM6 SeG36 COM7 SeG35 SeG34 SeG33 SeG32 SeG31 SeG30 SeG29 SeG28 SeG27 SeG26 SCLK1 AIN4 P16 AIN3 P17 AIN2 P20 AIN1 P...

Page 21: ... SCL0 SENA1 TOUTA5 CAPA5 P31 SDA0 SENB1 TOUTB5 CAPB5 P32 N C N C N C N C SCL1 SCL0 TOUTA6 CAPA6 P33 SDA1 SDA0 TOUTB6 CAPB6 P34 FOUT1 BFR P35 TOUT3 RFCLKO eXCl5 P36 TOUTN3 LFRO TOUT4 eXCl6 P37 FOUTH P40 P41 DSiO P42 DST2 P43 DClK N C N C N C N C SeG0 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 65 64 63 62 61 60 59...

Page 22: ...2 027 96 VSS 1 450 2 027 32 SEG25 1 550 2 027 97 AVDD 1 550 2 027 33 SEG26 1 999 1 530 98 P16 SCLK1 AIN4 1 999 1 570 34 SEG27 1 999 1 430 99 P17 AIN3 1 999 1 470 35 SEG28 1 999 1 330 100 P20 AIN2 1 999 1 370 36 SEG29 1 999 1 230 101 P21 AIN1 1 999 1 270 37 SEG30 1 999 1 130 102 P22 AIN0 1 999 1 170 38 SEG31 1 999 1 030 103 VDD 1 999 1 070 39 SEG32 1 999 0 930 104 P23 SENB0 1 999 0 970 40 SEG33 1 9...

Page 23: ... 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 VSS VC1 VC2 VC3 Ca CB N C N C COM0 COM1 COM2 COM3 SeG55 COM4 SeG54 COM5 SeG53 COM6 SeG52 COM7 SeG51 SeG50 SeG49 SeG48 SeG47 SeG46 SeG45 SeG44 SeG43 SeG42 SeG41 SeG40 SeG39 SeG38 SeG37 SeG36 SCLK1 AIN4 P16 AIN3 P...

Page 24: ... RFIN1 P27 SIN1 REF1 P30 SCL0 SENA1 P31 SDA0 SENB1 P32 BFR P53 LFRO P54 P55 P56 SCL1 SCL0 P33 SDA1 SDA0 P34 FOUT1 BFR P35 TOUT3 RFCLKO P36 TOUTN3 LFRO TOUT4 P37 FOUTH P40 P41 DSiO P42 DST2 P43 DClK N C SeG0 SeG1 SeG2 SeG3 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 ...

Page 25: ...027 95 P15 EXCL3 AIN5 1 350 2 027 31 SEG34 1 450 2 027 96 VSS 1 450 2 027 32 SEG35 1 550 2 027 97 AVDD 1 550 2 027 33 SEG36 1 999 1 530 98 P16 SCLK1 AIN4 1 999 1 570 34 SEG37 1 999 1 430 99 P17 AIN3 1 999 1 470 35 SEG38 1 999 1 330 100 P20 AIN2 1 999 1 370 36 SEG39 1 999 1 230 101 P21 AIN1 1 999 1 270 37 SEG40 1 999 1 130 102 P22 AIN0 1 999 1 170 38 SEG41 1 999 1 030 103 VDD 1 999 1 070 39 SEG42 1...

Page 26: ... 37 36 35 34 33 32 31 30 29 28 27 26 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 VSS VC1 VC2 VC3 Ca CB N C COM0 COM1 COM2 COM3 SeG39 COM4 SeG38 COM5 SeG37 COM6 SeG36 COM7 SeG35 SeG34 SeG33 SeG32 SeG31 SeG30 SeG29 SeG28 SeG27 SeG26 SCLK1 AIN4 P16 AIN3 P17 AIN2 P20 AIN1 P21 AIN0 P22 VDD SENB0 P23 SENA0 P24 REF0 P25 RFIN0 P26 VSS SOUT1 RFIN1 P27 SIN1 REF1 P30 SCL0 SENA...

Page 27: ...SDA0 SENB1 VSS P25 REF0 P23 SENB0 P17 AIN3 P15 eXCl3 AIN5 P14 eXCl2 AIN6 SeG6 SeG5 VSS VSS VSS VSS VSS VSS VSS VSS VDD P13 eXCl1 AIN7 P12 SIN0 SeG7 SeG8 VSS VSS VDD VDD P11 SOUT0 P10 SCLK0 SeG11 SeG10 SeG9 VSS VDD VDD P07 SPISS0 P06 SDI0 SeG14 SeG13 SeG12 VSS VSS P05 SDO0 P04 SPICLK0 P03 ADTRG SeG15 SeG16 VSS VSS VDD P02 eXCl0 P01 REMI P00 REMO SeG17 SeG18 VSS VSS VDD VDD TeST ReSeT SeG20 SeG21 Se...

Page 28: ...N C SCLK1 AIN4 P16 AIN3 P17 AIN2 P20 AIN1 P21 AIN0 P22 VDD SENB0 P23 SENA0 P24 REF0 P25 RFIN0 P26 VSS N C SOUT1 RFIN1 P27 SIN1 REF1 P30 SCL0 SENA1 P31 SDA0 SENB1 P32 SCL1 SCL0 P33 SDA1 SDA0 P34 FOUT1 BFR P35 TOUT3 RFCLKO P36 TOUTN3 LFRO TOUT4 P37 N C FOUTH P40 P41 DSiO P42 DST2 N C P43 DClK N C SeG0 N C 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 11...

Page 29: ...P15 EXCL3 AIN5 1 200 1 827 28 SEG25 1 300 1 827 87 VSS 1 300 1 827 29 N C 1 400 1 827 88 AVDD 1 400 1 827 30 N C 1 849 1 430 89 P16 SCLK1 AIN4 1 849 1 470 31 SEG26 1 849 1 330 90 P17 AIN3 1 849 1 370 32 N C 1 849 1 230 91 P20 AIN2 1 849 1 270 33 SEG27 1 849 1 130 92 P21 AIN1 1 849 1 170 34 N C 1 849 1 030 93 P22 AIN0 1 849 1 070 35 SEG28 1 849 0 930 94 VDD 1 849 0 970 36 SEG29 1 849 0 830 95 P23 S...

Page 30: ... function SPISS0 I SPI Ch 0 slave select signal input pin P10 I O I Pull up I O port pin with port input interrupt function SCLK0 I UART Ch 0 external clock input pin P11 I O I Pull up I O port pin with port input interrupt function SOUT0 O UART Ch 0 data output pin P12 I O I Pull up I O port pin with port input interrupt function SIN0 I UART Ch 0 data input pin P13 I O I Pull up I O port pin with...

Page 31: ... O port pin SDA1 I O I2C slave data input output pin SDA0 I O I2C master data input output pin TOUTB6 O T16A2 Ch 1 TOUT B signal output pin CAPB6 I T16A2 Ch 1 capture B trigger signal input pin P35 I O I Pull up I O port pin FOUT1 O OSC1 clock external output pin BFR I I2C slave bus free request input pin P36 I O I Pull up I O port pin EXCL5 I T16A2 Ch 0 external clock input pin TOUT3 O T16E Ch 0 ...

Page 32: ... O I Pull up I O port pin TOUTB6 O T16A2 Ch 1 TOUT B signal output pin CAPB6 I T16A2 Ch 1 capture B trigger signal input pin SEG0 35 O O L LCD segment output pins SEG36 39 O O L LCD segment output pins COM7 4 O LCD common output pins SEG40 51 O O L LCD segment output pins SEG52 55 O O L LCD segment output pins COM7 4 O LCD common output pins COM0 3 O O L LCD common output pins RESET I I Pull up In...

Page 33: ... Number of instructions 111 basic instructions 184 including variations Execution cycle Main instructions executed in one cycle Extended immediate instructions Immediate extended up to 24 bits Compact and fast instruction set optimized for development in C language Register set Eight 24 bit general purpose registers Two 24 bit special registers One 8 bit special register Memory space and bus Up to...

Page 34: ...Memory address post increment post decrement and pre decrement functions can be used rb rs rb rs rb rs sp imm7 rs General purpose register byte stack imm7 rs General purpose register byte memory ld ub rd rs General purpose register byte general purpose register zero extended rd rb Memory byte general purpose register zero extended Memory address post increment post decrement and pre decrement func...

Page 35: ...ition of general purpose register and immediate sp imm7 24 bit addition of SP and immediate adc rd rs 16 bit addition with carry between general purpose registers Supports conditional execution c executed if C 1 nc executed if C 0 adc c adc nc adc rd imm7 16 bit addition of general purpose register and immediate with carry sub rd rs 16 bit subtraction between general purpose registers Supports con...

Page 36: ...ion ext imm13 Extend operand in the following instruction Conversion cv ab rd rs Converts signed 8 bit data into 24 bits cv as rd rs Converts signed 16 bit data into 24 bits cv al rd rs Converts 32 bit data into 24 bits cv la rd rs Converts 24 bit data into 32 bits cv ls rd rs Converts 16 bit data into 32 bits Branch jpr jpr d sign10 PC relative jump Delayed branching possible rb jpa jpa d imm7 Ab...

Page 37: ... with address pre decremented sp Stack pointer sp sp imm7 Stack sp Stack with address post incremented sp Stack with address post decremented sp Stack with address pre decremented imm3 imm5 imm7 imm13 Unsigned immediate numerals indicating bit length sign7 sign10 Signed immediate numerals indicating bit length Reading PSR 2 4 The S1C17624 604 622 602 621 includes the MISC_PSR register for reading ...

Page 38: ...efault D0 PSRN PSR Negative N Flag Bit The value of the PSR N negative flag can be read out 1 R 1 0 R 0 default Processor information 2 5 The S1C17624 604 622 602 621 has the IDIR register shown below that allows the application software to identify CPU core type Processor iD Register iDiR Register name address Bit name Function Setting init R W Remarks Processor ID Register IDIR 0xffff84 8 bits D...

Page 39: ...ed UART Ch 0 1 reserved MISC registers MISC reserved Debug RAM area 64 bytes Internal RAM area 8K bytes 1 cycle Device size 32 bits 0x5440 0x5fff 0x5400 0x543f 0x53c0 0x53ff 0x53a0 0x53bf 0x5380 0x539f 0x5360 0x537f 0x5340 0x535f 0x5320 0x533f 0x5300 0x531f 0x52c0 0x52ff 0x52a0 0x52bf 0x5280 0x529f 0x5200 0x527f 0x5180 0x51ff 0x5140 0x517f 0x5120 0x513f 0x5100 0x511f 0x50e0 0x50ff 0x50c0 0x50df 0x...

Page 40: ... bits 8 bits Peripheral function Device size 1 The address range from 0x000fc0 to 0x000fff of the S1C17622 is an internal RAM area 2 The address range from 0x027ffc to 0x027fff of the S1C17602 is a reserved area 2 S1C17622 602 Memory Map Figure 3 0x4380 0x43ff 0x4360 0x437f 0x4340 0x435f 0x4320 0x433f 0x42e0 0x431f 0x4280 0x42df 0x4220 0x427f 0x4200 0x421f 0x4140 0x41ff 0x4100 0x413f 0x4040 0x40ff...

Page 41: ...ddress as the low order 24 bits number of bus cycles calculation example Number of bus cycles when the CPU accesses the display RAM area eight bit device set to two access cycles by a 16 bit read or write instruction 2 cycles 2 bus accesses 4 CCLK cycles Restrictions on access Size 3 1 1 The modules shown below have a restriction on the access size Appropriate instructions should be used in pro gr...

Page 42: ...r to protect the memory contents the Flash memory provides two protection features write protection and data read protection that can be configured for every 16K byte areas The write protection disables writing data to the configured area The data read protection disables reading data from the configured area the read value is al ways 0x0000 However it does not disable the instruction fetch operat...

Page 43: ...fff 1 Readable 0 Protected 1 R W D1 Flash data read protect bit for 0xc000 0xffff 1 Readable 0 Protected 1 R W D0 reserved 1 1 R W Always set to 1 Flash Protect Bits S1C17621 address Bit Function Setting init R W Remarks 0x17ffc 16 bits D15 2 reserved D1 Flash write protect bit for 0xc000 0xffff 1 Writable 0 Protected 1 R W D0 Flash write protect bit for 0x8000 0xbfff 1 Writable 0 Protected 1 R W ...

Page 44: ... and other data Note The 64 byte area at the end of the RAM S1C17624 604 0x1fc0 0x1fff S1C17602 0xfc0 0xfff is reserved for the on chip debugger When using the debug functions under application develop ment do not access this area from the application program This area can be used for applica tions of mass produced devices that do not need debugging The S1C17624 604 enables the RAM size used to ap...

Page 45: ...ult Reserved default 0x1 8KB default Reserved default Reserved Reserved Other Reserved Reserved Reserved Reserved Notes The MISC_IRAMSZ register is write protected The write protection must be overridden by writing 0x96 to the MISC_PROT register Note that the MISC_PROT register should normally be set to a value other than 0x96 except when writing to the MISC_IRAMSZ register Unnec essary programs m...

Page 46: ... SEGRAM 16 bit device 16 bit PWM timers T16A2 16 bit device Available only in the S1C17624 604 S1C17 Core i O area 3 6 The 1K byte area from address 0xfffc00 to address 0xffffff is the I O area for the CPU core in which the I O regis ters listed in the table below are located 6 1 I O Map S1C17 Core I O Area Table 3 Peripheral address Register name Function S1C17 Core I O 0xffff84 IDIR Processor ID...

Page 47: ... GND Note Be sure to supply the same voltage as VDD to the AVDD pin even if the analog circuit is not used Noise on the analog power lines decrease the A D converting precision so use a stabilized power supply and make the board pattern with consideration given to that internal Power Supply Circuit 4 3 The S1C17624 604 622 602 621 has a built in power supply circuit shown in Figure 4 3 1 to genera...

Page 48: ...ltage and operating mode or to reduce current consumption the power supply circuit is designed to be controlled with software Switching the operating mode The S1C17624 604 622 602 621 has two kinds of operating modes 1 Normal operating mode This mode is provided for running the application program VDD 1 8 to 3 6 V internal operating voltage VD1 1 8 V 2 Flash erase programming mode This mode is pro...

Page 49: ...veral 10 µs after the switching has completed When turning the high speed oscillator OSC3 IOSC on Set the regulator in heavy load protection mode im mediately before turning the oscillator on and maintain it until the oscillation stabilization wait time has elapsed When placing releasing the system into from HALT SLEEP mode at frequent intervals Maintain the regulator in heavy load protection mode...

Page 50: ...trol Register LCD_VREG Register name address Bit name Function Setting init R W Remarks LCD Voltage Regulator Control Register LCD_VREG 0x50a3 8 bits D7 5 reserved 0 when being read D4 LHVLD LCD heavy load protection mode 1 On 0 Off 0 R W D3 1 reserved 0 when being read D0 VCSEL VC reference voltage select 1 VC2 0 VC1 0 R W D 7 5 Reserved D4 LHVLD LCD Heavy Load Protection Mode Bit Sets the LCD sy...

Page 51: ...eads the reset vector reset handler start address from the beginning of the vector table and starts executing the program initial routine beginning with the read ad dress ReSeT Pin 5 1 1 By setting the RESET pin to low level the S1C17624 604 622 602 621 enters initial reset state In order to initial ize the S1C17624 604 622 602 621 for sure the RESET pin must be held at low for more than the presc...

Page 52: ...The CPU starts operating in synchronization with the IOSC internal oscillator clock after reset state is canceled Note The oscillation stabilization time described in this section does not include oscillation start time Therefore the time interval until the CPU starts executing instructions after power is turned on or SLEEP mode is canceled may be longer than that indicated in the figure below Boo...

Page 53: ... 16 UART Ch 0 interrupt 3 types 17 UART Ch 1 interrupt 3 types 18 IR remote controller REMC interrupt 3 types 19 SPI Ch 0 interrupt 2 types 20 I2C master I2CM interrupt 2 types 21 I2C slave I2CS interrupt 3 types 22 A D converter ADC10 interrupt 2 types 23 R F converter RFC interrupt 5 types Supports eight interrupt levels to prioritize the interrupt sources The ITC enables the interrupt level pri...

Page 54: ...ow 2 1 1 0x01 TTBR 0x04 Address misaligned interrupt Memory access instruction 2 0xfffc00 Debugging interrupt brk instruction etc 3 2 0x02 TTBR 0x08 NMI Watchdog timer overflow 2 4 3 0x03 TTBR 0x0c Reserved for C compiler 4 0x04 TTBR 0x10 P0 port interrupt P00 P07 port inputs High 1 5 0x05 TTBR 0x14 P1 port interrupt P10 P17 port inputs 6 0x06 TTBR 0x18 Stopwatch timer SWT interrupt 100 Hz timer si...

Page 55: ...errupts that share an interrupt vector Interrupt vector numbers 7 10 and 17 are shared with two different interrupt modules Interrupt vector 7 Clock timer CT and real time clock RTC S1C17624 604 Interrupt vector 10 LCD driver LCD and 16 bit PWM timer T16A2 Ch 0 S1C17624 604 Interrupt vector 17 I2C slave I2CS and UART Ch 1 The interrupt signals from the two modules are input to the ITC through an O...

Page 56: ...uest Processing 6 3 2 On receiving an interrupt signal from a peripheral module the ITC sends the interrupt request interrupt level and vector number signals to the S1C17 Core Vector numbers are determined by the ITC internal hardware for each interrupt cause as shown in Table 6 2 1 The interrupt level is a value used by the S1C17 Core to compare with the IL bits PSR This interrupt level is used i...

Page 57: ... the peripheral module The IE Interrupt Enable bit of the PSR Processor Status Register in the S1C17 Core has been set to 1 The cause of interrupt that has occurred has a higher interrupt level than the value set in the IL field of the PSR No other cause of interrupt having higher priority such as NMI has occurred If an interrupt cause that has been enabled in the peripheral module occurs the corr...

Page 58: ...on see Power Saving by Clock Control in the appendix chapter For the oscillator circuit and system clock statuses after HALT or SLEEP mode is canceled see the Clock Generator CLG chapter Control Register Details 6 7 7 1 List of ITC Registers Table 6 address Register name Function 0x4306 ITC_LV0 Interrupt Level Setup Register 0 Sets the P0 and P1 interrupt levels 0x4308 ITC_LV1 Interrupt Level Setu...

Page 59: ... an interrupt requests of higher priority occurs while the ITC outputs an interrupt request signal to the S1C17 Core before acceptance by the S1C17 Core the ITC alters the vector number and interrupt level signals to the setting details of the most recent interrupt The immediately preceding interrupt is held 7 2 Interrupt Level Bits Table 6 Register Bit interrupt ITC_LV0 0x4306 ILV0 2 0 D 2 0 P0 p...

Page 60: ...d from system clock 1 1 1 2 1 4 and 1 8 Controls the clock supply to the peripheral modules Turns the clocks on and off according to the CPU operating status RUN HALT or SLEEP Controls two clock outputs to external devices Figure 7 1 1 shows the clock system and CLG module configuration CCLK HSCLK HSCLK SYSCLK OSC1 OSC3 OSC1 OSC1 IOSC FOUT1 output circuit OSC3 oscillator 8 2 MHz IOSC oscillator 2 ...

Page 61: ...ate the main clock for high speed operation of the S1C17 Core and peripheral circuits The OSC1 oscilla tor generates a sub clock for timers and low power operations The IOSC clock is selected as the system clock after an initial reset Oscillator on off switching and system clock selection from IOSC OSC3 and OSC1 are controlled with software iOSC Oscillator 7 3 1 The IOSC oscillator initiates high ...

Page 62: ...pter CPU operation start time at initial reset IOSC oscillation start time max IOSC oscillation stabilization wait time 64 cycles When the system clock is switched to IOSC immediately after turning the IOSC oscillator on the IOSC clock is supplied to the system after the IOSC clock system supply wait time indicated below at a maximum has elapsed If the power supply voltage VDD has stabilized suffi...

Page 63: ...ime indicated below at a maxi mum has elapsed For the oscillation start time see the Electrical Characteristics chapter OSC3 clock system supply wait time OSC3 oscillation start time max OSC3 oscillation sta bilization wait time Note Oscillation stability will vary depending on the resonator and other external components Carefully consider the OSC3 oscillation stabilization wait time before reduci...

Page 64: ...lock is not supplied to other peripheral modules if OSC1EN 0 When RTCCE 0 the OSC1 stops in SLEEP mode regardless of how OSC1EN is set After an initial reset OSC1EN and RTCCE are both set to 0 and the OSC1 oscillator circuit is halted 3 3 1 OSC1 Oscillator Operating Status S1C17624 604 in normal operation Table 7 OSC1en RTCCe OSC1 oscillator Clock supply to peripheral modules Clock supply to RTC 1...

Page 65: ... wait time if necessary OSC3WT 1 0 2 Turn the OSC3 oscillator on if it is off OSC3EN 1 3 Select the OSC3 clock as HSCLK HSCLKSEL 1 4 Select HSCLK OSC3 clock as the system clock CLKSRC 0 5 Turn the IOSC or OSC1 oscillator off if peripheral modules and FOUT1 output circuit have not used the IOSC or OSC1 clock Switching the system clock to OSC1 from iOSC or OSC3 1 Turn the OSC1 oscillator on OSC1EN 1...

Page 66: ... reduce cur rent consumption operate the S1C17 Core with the slowest possible clock speed The halt instruction can be ex ecuted to stop the clock supply from the CLG to the S1C17 Core for power savings HSCLK OSC1 CCLK Clock gear 1 1 1 8 Gate S1C17 Core Gear selection System clock HALT 5 1 CCLK Supply System Figure 7 Clock gear settings CCLKGR 1 0 CLG_CCLK register is used to select the gear ratio ...

Page 67: ...The PCLK supply cannot be disabled if one or more peripheral modules in these list must be operated The PCLK supply can be disabled if all the periph eral circuits in these list can be stopped 8 bit timer T8F UART SPI I2C master I2CM I2C slave I2CS 16 bit PWM timer T16E I O port P MISC register MISC Power generator VD1 Supply voltage detector SVD IR remote controller REMC A D converter ADC10 Inter...

Page 68: ...uTh output control FOUTH is a divided HSCLK IOSC or OSC3 clock FOuTh clock frequency selection Three different clock output frequencies can be selected Select the division ratio for the HSCLK clock us ing FOUTHD 1 0 OSC_FOUT register 7 1 FOUTH clock HSCLK Division Ratio Selection Table 7 FOuThD 1 0 Division ratio 0x3 Reserved 0x2 1 4 0x1 1 2 0x0 1 1 Default 0x0 Clock output control The clock outpu...

Page 69: ...LK PCLK Control Register Controls the PCLK supply 0x5081 CLG_CCLK CCLK Control Register Configures the CCLK division ratio The CLG module registers are described in detail below These are 8 bit registers Note When data is written to the registers the Reserved bits must always be written as 0 and not 1 Prescaler Control Register PSC_CTL Register name address Bit name Function Setting init R W Remar...

Page 70: ...le 7 HSCLK Conditions iOSC OSC3 OSC1 hSClKSel System clock On On On IOSC OSC3 or OSC1 On Off On 0 IOSC or OSC1 Off On On 1 OSC3 or OSC1 When switching the HSCLK source IOSC OSC3 always make sure that PCKEN 1 0 CLG_PCLK register is set to 0x3 before writing to HSCLKSEL The oscillator circuit selected as the system clock source cannot be turned off Continuous write read access to CLKSRC is prohibite...

Page 71: ...lation stabilization wait time D 5 4 OSC3WT 1 0 OSC3 Wait Cycle Select Bits An oscillation stabilization wait time is set to prevent malfunctions due to unstable clock operation at the start of OSC3 oscillation The OSC3 clock is not supplied to the system immediately after OSC3 oscillation starts e g when the OSC3 oscillator is turned on with software until the time set here has elapsed 9 4 OSC3 O...

Page 72: ...FEN 0x5062 8 bits D7 2 reserved 0 when being read D1 RSTFE Reset noise filter enable 1 Enable 0 Disable 1 R W D0 NMIFE NMI noise filter enable 1 Enable 0 Disable 0 R W D 7 2 Reserved D1 RSTFE Reset Noise Filter Enable Bit Enables or disables the RESET input noise filter 1 R W Enabled noise filtering default 0 R W Disabled bypass This should normally be enabled D0 NMIFE NMI Noise Filter Enable Bit ...

Page 73: ... the output PCLK Control Register CLG_PCLK Register name address Bit name Function Setting init R W Remarks PCLK Control Register CLG_PCLK 0x5080 8 bits D7 2 reserved 0 when being read D1 0 PCKEN 1 0 PCLK enable PCKEN 1 0 PCLK supply 0x3 R W 0x3 0x2 0x1 0x0 Enable Not allowed Not allowed Disable D 7 2 Reserved D 1 0 PCKEN 1 0 PCLK Enable Bits Enables or disables clock PCLK supply to the internal p...

Page 74: ...ped Notes Do not set PCKEN 1 0 to 0x2 or 0x1 and PRUN PSC_CTL register to 0 since doing so will stop the operation of certain peripheral modules The interrupt controller ITC needs PCLK only when the register is set CCLK Control Register CLG_CCLK Register name address Bit name Function Setting init R W Remarks CCLK Control Register CLG_CCLK 0x5081 8 bits D7 2 reserved 0 when being read D1 0 CCLKGR ...

Page 75: ...to both counters Includes read buffers to prevent carry over at reading Capable of controlling the starting and stopping of time clocks 24 hour or 12 hour mode can be selected A 30 second correction function can be implemented in software Periodic interrupts are possible Interrupt period can be selected from 1 512 second 1 256 second 1 128 second 1 64 second 1 second 1 min ute or 1 hour Level edge...

Page 76: ...ster 1 hour counter This 4 bit BCD counter counts in units of hours It counts from 0 to 9 with 1 carried over from the 10 min ute counter This counter is reset to 0 after 9 and outputs a carry over of 1 to the 10 hour counter Depending whether 12 hour or 24 hour mode is selected the counter is reset at 12 o clock or 24 o clock The count data is read out and written using RTCHL 3 0 RTC_HOUR registe...

Page 77: ...years It counts from 0 to 9 with 1 carried over from the 1 year counter The count data is read out and written using RTCYH 3 0 RTC_YEAR register Days of week counter This is a septenary counter that counts from 0 to 6 representing the days of the week It counts with the same timing as the 1 day counter The count data is read out and written using RTCWK 2 0 RTC_WEEK register The correspondence betw...

Page 78: ...ce 8 3 2 Immediately after power on the contents of RTC registers are indeterminate After powering on follow the proce dure below to let the RTC start ticking the time Later sections detail the contents of each control 1 Power on 2 System initialization processing Initialize the system If any peripheral module other than RTC uses the OSC1 clock turn the OSC1 oscillator circuit on using the CLG reg...

Page 79: ...ates as April 31 or February 29 2006 Even if such settings are made the counters operate normally so that when 1 is carried over from the hour counter to the 1 day counter the day counter counts up to the first day of the next month For April 31 the day counter counts up to May 1 for February 29 2006 the day counter counts up to March 1 2006 If any counter must be rewritten while operating there i...

Page 80: ...HLD to 0 If 1 is being carried over when data is being written to a counter in the hold state 1 second is automatically added to correct the counter values when RTCHLD is reset to 0 This correction is only effective for 1 second and no correction is conducted on the carry encountered in the second time and on In this case the timekeep ing data gets out of order Therefore be sure to reset RTCHLD to...

Page 81: ... counter values Always make sure that RTCBSY is set to 0 before writing 1 to RTCADJ RTCADJ 1 RTCADJ read RTCADJ 0 No Yes RTCADJ 1 RTCADJ read RTCADJ 0 No Yes 4 ms wait RTCHLD 1 RTCBSY read RTCHLD 0 RTCBSY 0 No a B Yes RTCHLD 1 RTCBSY read RTCHLD 0 RTCBSY 0 No Yes 4 ms wait 3 6 1 Procedure for Executing 30 second Correction Figure 8 Counter Read 8 3 7 In order to prevent carry over during reading c...

Page 82: ...d from the CLG If a cause of interrupt occurs when the bus clock has not been supplied such as in SLEEP mode the RTC switches the interrupt mode to level sensed and sets the interrupt signal to the active level from occurrence of the interrupt cause until the bus clock supply is started enabling and disabling interrupts The RTC interrupt requests output to the ITC are enabled by setting RTCIEN RTC...

Page 83: ...indeterminate when power is turned on and are not initialized to specific values by initial reset These registers should be initialized in software If 1 is being carried over when the counters are accessed for read the correct counter value may not be read out Moreover attempting to write to a counter or other control register may corrupt the counter value Therefore do not write to counters while ...

Page 84: ...over the value of this bit is indeterminate after power on and is not initialized to 0 by initial reset To prevent the occurrence of unwanted RTC inter rupts be sure to reset this bit in software after power on and initial reset RTC Interrupt Mode Register RTC_INTMODE Register name address Bit name Function Setting init R W Remarks RTC Interrupt Mode Register RTC_INTMODE 0x5141 8 bits D7 5 reserve...

Page 85: ...its D7 5 reserved 0 when being read D4 RTC24H 24H 12H mode select 1 24H 0 12H X 0 R W D3 reserved 0 when being read D2 RTCADJ 30 second adjustment 1 Adjust 0 X 0 R W D1 RTCSTP Divider run stop control 1 Stop 0 Run X 0 R W D0 RTCRST Software reset 1 Reset 0 X 0 R W Init indicates the value set after a software reset RTCRST 1 0 is performed D 7 5 Reserved D4 RTC24H 24H 12H Mode Select Bit This bit s...

Page 86: ...e contents of all counters are newly set again D0 RTCRST Software Reset Bit This bit resets the divider and output signals 1 R W Reset 0 R W Negate reset software reset value To perform software reset write 1 to RTCRST and then write 0 The software reset clears the 32 kHz to 2 Hz divider bits negates the interrupt request signal and ini tializes some control bits When setting up the RTC first perf...

Page 87: ...of counters to be checked and the counters held intact 1 R W Checks for busy state Holds counters 0 R W Normal operation software reset value For the operation of this bit see the description of RTCBSY above RTC Second Register RTC_SEC Register name address Bit name Function Setting init R W Remarks RTC Second Register RTC_SEC 0x5144 8 bits D7 reserved 0 when being read D6 4 RTCSH 2 0 RTC 10 secon...

Page 88: ...gain D7 Reserved D6 RTCAP AM PM Indicator Bit When 12 hour mode is selected this bit indicates A M or P M 1 R W P M 0 R W A M This bit is only effective when RTC24H RTC_CNTL0 register is set to 0 12 hour mode When 24 hour mode is selected this bit is fixed to 0 In this case do not write 1 to RTCAP Note The RTCAP bit keeps the current set value even if RTC24H RTC_CNTL0 register is changed from 12 h...

Page 89: ...ot affect the counter values This register retains the value set before a software reset is performed Notes Data should not be read from or written to the counters while 1 is being carried over See Section 8 3 5 Counter Hold and Busy Flag and Section 8 3 7 Counter Read Rewriting RTC24H RTC_CNTL0 register may corrupt the count data in this register Therefore after changing the RTC24H setting be sur...

Page 90: ...sday Monday Sunday Software reset RTCRST 1 0 does not affect the counter values This register retains the value set before a software reset is performed Notes Data should not be read from or written to the counters while 1 is being carried over See Section 8 3 5 Counter Hold and Busy Flag and Section 8 3 7 Counter Read Rewriting RTC24H RTC_CNTL0 register may corrupt the count data in this register...

Page 91: ...put interface levels selectable with software CMOS Schmitt level or CMOS level The P0 and P1 ports can generate input interrupts at the signal edge selected with software The P0 and P1 ports include a chattering filter Can generate an initial reset by entering low level simultaneously to the P0 ports selected with software All port provide a port function select bit to configure the pin function f...

Page 92: ...X 1 0 P20_23PMUX P21 AIN1 ADC10 P21MUX 1 0 P20_23PMUX P22 AIN0 ADC10 P22MUX 1 0 P20_23PMUX P23 SENB0 RFC P23MUX 1 0 P20_23PMUX P24 SENA0 RFC P24MUX 1 0 P24_27PMUX P25 REF0 RFC P25MUX 1 0 P24_27PMUX P26 RFIN0 RFC P26MUX 1 0 P24_27PMUX P27 SOUT1 UART RFIN1 RFC P27MUX 1 0 P24_27PMUX P30 SIN1 UART REF1 RFC P30MUX 1 0 P30_33PMUX P31 SCL0 I2CM SENA1 RFC TOUTA5 CAPA5 T16A2 3 P31MUX 1 0 P30_33PMUX P32 SDA...

Page 93: ... impedance status pull up off Output and input are both disabled The value read from PxINy input data is 0 0 0 1 The pin is placed into high impedance status pull up on Output and input are both disabled The value read from PxINy input data is 0 The input output direction of ports with a peripheral module function selected is controlled by the peripheral module PxOENy and PxIENy settings are ignor...

Page 94: ...able 9 I O port S1C17624 622 S1C17604 602 621 CMOS Schmitt level PxSMy 1 CMOS level PxSMy 0 CMOS Schmitt level PxSMy 1 CMOS level PxSMy 0 P00 P07 Selectable Selectable Selectable Selectable P10 P15 Selectable Selectable Selectable Selectable P16 P17 Fixed Fixed P20 P27 Fixed Fixed P30 P37 Fixed Fixed P40 Fixed Fixed DSIO P41 Fixed Fixed DST2 P42 Fixed Fixed DCLK P43 P44 P47 Selectable Selectable P...

Page 95: ...of twice the check time for stabilizing the operation status Before enabling the interrupt make sure that the stabilization time has elapsed Port input interrupt 9 7 Px port interrupt request to ITC Px P0 and P1 Chattering filter Interrupt flag Interrupt enable Interrupt edge selection Px0 PxCF1 2 0 PxEDGE0 PxIF0 PxIE0 Px7 PxCF2 2 0 PxEDGE7 PxIF7 PxIE7 7 1 Port Input Interrupt Circuit Configuratio...

Page 96: ...Registers Table 9 address Register name Function 0x5200 P0_IN P0 Port Input Data Register P0 port input data 0x5201 P0_OUT P0 Port Output Data Register P0 port output data 0x5202 P0_OEN P0 Port Output Enable Register Enables P0 port outputs 0x5203 P0_PU P0 Port Pull up Control Register Controls the P0 port pull up resistor 0x5204 P0_SM P0 Port Schmitt Trigger Control Register Controls the P0 port ...

Page 97: ...Selects the P0 3 0 port functions 0x52a1 P04_07PMUX P0 7 4 Port Function Select Register Selects the P0 7 4 port functions 0x52a2 P10_13PMUX P1 3 0 Port Function Select Register Selects the P1 3 0 port functions 0x52a3 P14_17PMUX P1 7 4 Port Function Select Register Selects the P1 7 4 port functions 0x52a4 P20_23PMUX P2 3 0 Port Function Select Register Selects the P2 3 0 port functions 0x52a5 P24...

Page 98: ...5252 8 bits D7 0 PxOEN 7 0 Px 7 0 port output enable 1 Enable 0 Disable 0 R W Notes The PxOENy bits for unavailable ports are reserved and always read as 0 P43 can only be used as an output port For how to configure P43 see the P43MUX P40_43PMUX register description D 7 0 PxOEN 7 0 Px 7 0 Port Output Enable Bits Enables or disables port outputs 1 R W Enabled 0 R W Disabled default PxOENy is the ou...

Page 99: ...chmitt 0 1 R Always enabled P4 Port Schmitt Trigger Control Register P4_SM 0x5244 8 bits D7 4 P4SM 7 4 P4 7 4 port Schmitt trigger input enable 1 Enable Schmitt 0 Disable CMOS 1 R W D 7 4 reserved in S1C17604 602 621 D3 0 P4SM 3 0 P4 3 0 port Schmitt trigger input enable 1 Enable Schmitt 0 1 R Always enabled P5 Port Schmitt Trigger Control Register P5_SM S1C17624 622 0x5254 8 bits D7 reserved 0 wh...

Page 100: ... set to 0 Px Port Interrupt Flag Registers Px_IFLG Register name address Bit name Function Setting init R W Remarks Px Port Interrupt Flag Register Px_IFLG 0x5207 0x5217 8 bits D7 0 PxIF 7 0 Px 7 0 port interrupt flag 1 Cause of interrupt occurred 0 Cause of interrupt not occurred 0 R W Reset by writing 1 Note The PxIFLG registers are available only for P0 and P1 ports D 7 0 PxIF 7 0 Px 7 0 Port I...

Page 101: ...e a chattering filter circuit for key entry that can be disabled or enabled with a check time specified individually for the four Px 3 0 and Px 7 4 ports using PxCF1 2 0 and PxCF2 2 0 respectively 9 2 Chattering Filter Function Settings Table 9 PxCF1 2 0 PxCF2 2 0 Check time 0x7 16384 fPCLK 8 ms 0x6 8192 fPCLK 4 ms 0x5 4096 fPCLK 2 ms 0x4 2048 fPCLK 1 ms 0x3 1024 fPCLK 512 µs 0x2 512 fPCLK 256 µs ...

Page 102: ...s set to 0x3 an initial reset is performed when the four ports P00 to P03 are simultaneously set to Low level Set P0KRST 1 0 to 0x0 when this reset function is not used Note The P0 port key entry reset function is disabled at initial reset and cannot be used for power on reset Px Port Input Enable Registers Px_IEN Register name address Bit name Function Setting init R W Remarks Px Port Input Enabl...

Page 103: ...0 port function select P00MUX 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved reserved REMO P00 The P00 to P03 port pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 P03MUX 1 0 P03 Port Function Select Bits 0x3 R W Reserved 0x2 R W Reserved 0x1 R W ADTRG ADC10 0x0 R W P03 default D 5 4 P02MUX 1 0 P02 Port Function Select Bits 0x3 R W Reserved...

Page 104: ...1 0x0 reserved reserved SDO0 P05 D1 0 P04MUX 1 0 P04 port function select P04MUX 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved reserved SPICLK0 P04 The P04 to P07 port pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 P07MUX 1 0 P07 Port Function Select Bits 0x3 R W Reserved 0x2 R W Reserved 0x1 R W SPISS0 SPI Ch 0 0x0 R W P07 default D 5 4...

Page 105: ...tion select P10MUX 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved reserved SCLK0 P10 The P10 to P13 port pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 P13MUX 1 0 P13 Port Function Select Bits 0x3 R W Reserved 0x2 R W AIN7 ADC10 0x1 R W Reserved 0x0 R W P13 EXCL1 T16 Ch 1 default To use the P13 pin for EXCL1 input P1OEN3 P1_OEN register m...

Page 106: ...6 reserved P14 EXCL2 The P14 to P17 port pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 P17MUX 1 0 P17 Port Function Select Bits 0x3 R W Reserved 0x2 R W Reserved 0x1 R W AIN3 ADC10 0x0 R W P17 default D 5 4 P16MUX 1 0 P16 Port Function Select Bits 0x3 R W Reserved 0x2 R W AIN4 ADC10 0x1 R W SCLK1 UART Ch 1 0x0 R W P16 default D 3 2 P15M...

Page 107: ...0x3 0x2 0x1 0x0 reserved reserved AIN1 P21 D1 0 P20MUX 1 0 P20 port function select P20MUX 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved reserved AIN2 P20 The P20 to P23 port pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 P23MUX 1 0 P23 Port Function Select Bits 0x3 R W Reserved 0x2 R W Reserved 0x1 R W SENB0 RFC 0x0 R W P23 default D 5 ...

Page 108: ... 0x2 0x1 0x0 reserved reserved REF0 P25 D1 0 P24MUX 1 0 P24 port function select P24MUX 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved reserved SENA0 P24 The P24 to P27 port pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 P27MUX 1 0 P27 Port Function Select Bits 0x3 R W Reserved 0x2 R W RFIN1 RFC 0x1 R W SOUT1 UART Ch 1 0x0 R W P27 default...

Page 109: ... Function 0x0 R W 0x3 0x2 0x1 0x0 reserved REF1 SIN1 P30 The P30 to P33 port pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 P33MUX 1 0 P33 Port Function Select Bits 0x3 R W TOUTA6 T16A2 Ch 1 comparator mode or CAPA6 T16A2 Ch 1 capture mode Selectable only in the S1C17624 604 0x2 R W SCL0 I2CM 0x1 R W SCL1 I2CS 0x0 R W P33 default D 5 4 P...

Page 110: ...w the pins are used D 7 6 P37MUX 1 0 P37 Port Function Select Bits 0x3 R W TOUT4 T8OSC1 0x2 R W LFRO LCD 0x1 R W TOUTN3 T16E Ch 0 0x0 R W P37 EXCL6 T16A2 Ch 1 default EXCL6 is available only in the S1C17624 604 To use the P37 pin for EXCL6 input P3OEN7 P3_OEN register must be set to 0 and P3IEN7 P3_IEN register must be set to 1 In addition to these settings EXCL6S P54_56PMUX register must be set t...

Page 111: ...rt pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 P43MUX 1 0 P43 Port Function Select Bits 0x3 R W Reserved 0x2 R W Reserved 0x1 R W P43 0x0 R W DCLK DBG default P43 is an output only port and no external signal cannot be input To use P43 as a general purpose output port make the following settings 1 Set P4OEN3 P4_OEN register to 1 outpu...

Page 112: ... Function 0x0 R W 0x3 0x2 0x1 0x0 reserved reserved SCL1 P44 Note This register is effective only in the S1C17624 622 The P44 to P47 port pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 P47MUX 1 0 P47 Port Function Select Bits 0x3 R W Reserved 0x2 R W Reserved 0x1 R W TOUT4 T8OSC1 0x0 R W P47 EXCL5 T16A2 Ch 0 default EXCL5 is available on...

Page 113: ...This register is effective only in the S1C17624 622 The P50 to P53 port pins are shared with the peripheral module pins This register is used to select how the pins are used D 7 6 P53MUX 1 0 P53 Port Function Select Bits 0x3 R W Reserved 0x2 R W Reserved 0x1 R W BFR I2CS 0x0 R W P53 default D 5 4 P52MUX 1 0 P52 Port Function Select Bits 0x3 R W Reserved 0x2 R W TOUTB5 T16A2 Ch 0 comparator mode or...

Page 114: ...tive only in the S1C17624 622 The P54 to P56 port pins are shared with the peripheral module pins This register is used to select how the pins are used D7 EXCL6S EXCL6 Input Select Bit Selects a port to be used as the EXCL6 input Selectable only in the S1C17624 1 R W P50 EXCL6 0 R W P37 EXCL6 default D6 EXCL5S EXCL5 Input Select Bit Selects a port to be used as the EXCL5 input Selectable only in t...

Page 115: ...s To UART Ch 0 from Ch 0 To UART Ch 1 from Ch 1 To ITC PRESER Timer reset Down counter T8F_TCx Control circuit Count mode select TRMD Fine mode setting TFMD 3 0 Fine mode 8 bit timer Ch x PCLK Divider 1 1 1 16K CLG 1 1 T8F Configuration 1 Channel Figure 10 Each channel of the T8F module consists of an 8 bit presettable down counter and an 8 bit reload data register holding the preset value The tim...

Page 116: ...rflows the timer presets the reload data register value into the counter and continues the count Thus the timer periodically outputs an underflow pulse T8F should be set to this mode to generate periodic interrupts or to generate a serial transfer clock One shot mode TRMD 1 Setting TRMD to 1 sets T8F to one shot mode In this mode the timer stops automatically as soon as the counter underflows This...

Page 117: ...peat See Section 10 3 3 Calculate the initial counter value and set it to the reload data register See Section 10 4 4 Reset the timer to preset the counter to the initial value See Section 10 5 5 When using timer interrupts set the interrupt level and enable interrupts for the relevant timer channel See Section 10 9 To start the timer write 1 to PRUN T8F_CTLx register The timer starts counting dow...

Page 118: ...the following equations to calculate the reload data register value for obtaining the desired transfer rate clk_in bps T8F_TR 1 16 TFMD clk_in T8F_TR TFMD 16 16 bps bps Transfer rate bits second clk_in Count clock PCLK 1 to PCLK 16384 frequency Hz T8F_TR Reload data 0 to 255 TFMD Fine mode setting 0 to 15 Fine Mode 10 8 Fine mode provides a function that minimizes transfer rate errors T8F can outp...

Page 119: ...nting insertion of delay cycles T8F interrupts 10 9 Each channel of the T8F module outputs an interrupt request to the interrupt controller ITC when the counter un derflows underflow interrupt When the counter underflows the interrupt flag T8FIF T8F_INTx register which is provided for each channel in the T8F module is set to 1 At the same time an interrupt request is sent to the ITC if T8FIE T8F_I...

Page 120: ... Reserved bits must always be written as 0 and not 1 T8F Ch x Count Clock Select Registers T8F_CLKx Register name address Bit name Function Setting init R W Remarks T8F Ch x Count Clock Select Register T8F_CLKx 0x4200 0x4280 16 bits D15 4 reserved 0 when being read D3 0 DF 3 0 Count clock division ratio select DF 3 0 Division ratio 0x0 R W Source clock PCLK 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 ...

Page 121: ...be written to T8F Ch x Control Registers T8F_CTLx Register name address Bit name Function Setting init R W Remarks T8F Ch x Control Register T8F_CTLx 0x4206 0x4286 16 bits D15 12 reserved 0 when being read D11 8 TFMD 3 0 Fine mode setup 0x0 to 0xf 0x0 R W Set a number of times to insert delay into a 16 underflow period D7 5 reserved 0 when being read D4 TRMD Count mode select 1 One shot 0 Repeat 0...

Page 122: ...the counter to the reload data register value then stops when an underflow occurs Set the timer to this mode to set a specific wait time D 3 2 Reserved D1 PRESER Timer Reset Bit Resets the timer 1 W Reset 0 W Ignored 0 R Always 0 when read default Writing 1 to this bit presets the counter to the reload data value D0 PRUN Timer Run Stop Control Bit Controls the timer RUN STOP 1 R W Run 0 R W Stop d...

Page 123: ...T8F Interrupt Flag Bit Indicates whether the cause of counter underflow interrupt has occurred or not 1 R Cause of interrupt has occurred 0 R No cause of interrupt has occurred default 1 W Flag is reset 0 W Ignored T8FIF is the T8F module interrupt flag that is set to 1 when the counter underflows T8FIF is reset by writing 1 ...

Page 124: ...verter from Ch 0 To SPI from Ch 1 To I2C master from Ch 2 PCLK PRESER Timer reset Down counter T16_TCx Control circuit Count mode select TRMD 16 bit timer Ch x Divider 1 1 1 16K CLG EXCLx External input signal polarity select CKACTV Operating mode select CKSL 1 0 1 1 T16 Configuration 1 Channel Figure 11 Each channel of the T16 module consists of a 16 bit presettable down counter and a 16 bit relo...

Page 125: ...Pulse width measurement mode measures the external input pulse width using an internal clock The operating mode is selected using CKSL 1 0 T16_CTLx register 3 1 Operating Mode Selection Table 11 CKSl 1 0 Operating mode 0x3 Reserved 0x2 Pulse width measurement mode 0x1 External clock mode 0x0 Internal clock mode Default 0x0 internal Clock Mode 11 3 1 Internal clock mode uses a divided PCLK clock as...

Page 126: ... uses the falling edge when set to 0 External input clock PRUN Counter CKACTV 1 Counter CKACTV 0 n 1 n 2 n 3 n 4 n 5 n 6 n 7 n 8 n 9 n 10 n n 1 n 2 n 3 n 4 n 5 n 6 n 7 n 8 n 9 n 10 n 3 2 1 Counting in External Clock Mode Figure 11 Pulse Width Measurement Mode 11 3 3 In pulse width measurement mode when pulses with the specified polarity are input from the external clock port the internal clock is ...

Page 127: ...A D conversion triggers at desired intervals or to generate a serial transfer clock One shot mode TRMD 1 Setting TRMD to 1 sets T16 to one shot mode In this mode the timer stops automatically as soon as the counter underflows This means only one interrupt can be generated after the timer starts Note that the timer presets the reload data register value to the counter then stops after an underflow ...

Page 128: ...e and set it to the reload data register See Section 11 5 5 Reset the timer to preset the counter to the initial value See Section 11 6 6 When using timer interrupts set the interrupt level and enable interrupts for the relevant timer channel See Section 11 9 To start the timer write 1 to PRUN T16_CTLx register The timer starts counting down from the initial value or from the current counter value...

Page 129: ...Ch 0 output clock A D converter T16 Ch 1 output clock SPI T16 Ch 2 output clock I2C master Use the following equations to calculate the reload data register value for obtaining the desired transfer rate or A D conversion interval ct_clk SPI TR 1 bps 2 ct_clk I2C master TR 1 bps 4 ct_clk adi A D converter TR 1 2 ct_clk Count clock frequency Hz TR Reload data 0 65535 bps Transfer rate bits s adi A D...

Page 130: ...T16_TR1 T16 Ch 1 Reload Data Register Sets reload data 0x4244 T16_TC1 T16 Ch 1 Counter Data Register Counter data 0x4246 T16_CTL1 T16 Ch 1 Control Register Sets the timer mode and starts stops the timer 0x4248 T16_INT1 T16 Ch 1 Interrupt Control Register Controls the interrupt 0x4260 T16_CLK2 T16 Ch 2 Count Clock Select Register Selects a count clock 0x4262 T16_TR2 T16 Ch 2 Reload Data Register Se...

Page 131: ... frequency determine the time elapsed from the point at which the timer starts until the underflow occurs or between underflows The time determined is used to obtain the desired wait time the intervals between periodic interrupts or A D conversion trigger and the programmable serial interface transfer clock T16 Ch x Counter Data Registers T16_TCx Register name address Bit name Function Setting ini...

Page 132: ...6 to be used as an event counter Timer operations other than the input clock are the same as for internal clock mode In pulse width measurement mode when pulses with the specified polarity are input from the external clock port the internal clock is fed only while the input pulse is active enabling counting This enables T16 to generate an interrupt when a pulse with the specified width or greater ...

Page 133: ...ble 1 Enable 0 Disable 0 R W D7 1 reserved 0 when being read D0 T16IF T16 interrupt flag 1 Cause of interrupt occurred 0 Cause of interrupt not occurred 0 R W Reset by writing 1 D 15 9 Reserved D8 T16IE T16 Interrupt Enable Bit Enables or disables interrupts caused by counter underflows for each channel 1 R W Interrupt enabled 0 R W Interrupt disabled default Setting T16IE to 1 enables T16 interru...

Page 134: ...r 1 1 1 16K CLG Compare data A buffer T16E_CAx Compare data B buffer T16E_CBx Compare B signal Comparator 16 bit PWM timer T16E Ch x T16EDF 3 0 CLKSEL T16ERUN OUTEN INVOUT T16ERST CBUFEN 1 1 T16E Module Configuration Figure 12 The T16E module includes a 16 bit up counter T16E_TCx register two 16 bit compare data registers T16E_CAx and T16E_CBx registers and the corresponding buffers The 16 bit cou...

Page 135: ...ting mode is selected using CLKSEL T16E_CTLx register Setting CLKSEL to 0 default selects internal clock mode while setting to 1 selects external clock mode internal Clock Mode 12 3 1 Internal clock mode uses a divided PCLK clock as the count clock The count clock is generated by dividing the PCLK clock into 1 1 to 1 16K The division ratio can be selected from the 15 types shown below using T16EDF...

Page 136: ...mpare data A is written to CA 15 0 T16E_CAx register Compare data B is written to CB 15 0 T16E_CBx register When CBUFEN is set to 0 the compare data register values can be read or written directly by these registers When CBUFEN is set to 1 data is read from and written to these registers via the compare data buffers The buffer contents are loaded into the compare data registers when the counter is...

Page 137: ...te TOUTx and TOUTNx signals using the compare match signals Figure 12 7 1 shows the T16E clock output circuit Logic INITOL Compare A Compare B Clock TOUTx TOUTNx D Q Q OUTEN INVOUT 7 1 T16E Clock Output Circuit Figure 12 initial output level setting The default output level is 0 low level while the TOUTx clock output is Off TOUTNx output level is high This can be changed to 1 TOUTx high level TOUT...

Page 138: ...ta B set in the T16E_CBx register the counter is reset and the output pin is returned to low level A cause of compare B interrupt is also occurred at the same time The TOUTNx pin outputs the inverted signals described above TOuTx output when inVOuT 1 active low The TOUTx pin outputs high level inverted value of the initial output level at output start until the counter matches the compare data A s...

Page 139: ...interrupt Compare B interrupt A T16E timer channel outputs a single interrupt signal shared by the above interrupt causes to the interrupt control ler ITC Read the interrupt flags in the T16E module to identify the interrupt cause that has been occurred Compare a interrupt This interrupt request is generated when the counter matches the compare data A register value during count ing It sets the in...

Page 140: ... A buf fer The buffer contents are loaded into the compare data A register when the counter is reset The data set is compared against the counter data and a cause of compare A interrupt is generated if the contents match The timer output waveform changes at the same time rises when INVOUT T16E_ CTLx register 0 or falls when INVOUT 1 These processes do not affect the counter data or count operation...

Page 141: ...o fine mode and the output clock duty becomes ad justable in count clock half cycle steps When SELFM is set to 0 normal clock output is performed D5 CBUFEN Comparison Buffer Enable Bit Enables or disables writing to the compare data buffer 1 R W Enabled 0 R W Disabled default When CBUFEN is set to 1 compare data is read and written via the compare data buffer The buffer contents are loaded into th...

Page 142: ...o T16ERUN and stops when 0 is written The counter data is retained when stopped until the subsequent reset or run Counting can be resumed when switched from stop to run from the data retained T16E Ch x Clock Division Ratio Select Register T16E_DFx Register name address Bit name Function Setting init R W Remarks T16E Ch x Clock Division Ratio Select Register T16E_DFx 0x5308 16 bits D15 4 reserved 0...

Page 143: ...t Setting CAIE to 1 enables compare A interrupt requests to the ITC Setting it to 0 disables interrupts T16E Ch x Interrupt Flag Register T16E_IFLGx Register name address Bit name Function Setting init R W Remarks T16E Ch x Interrupt Flag Register T16E_IFLGx 0x530c 16 bits D15 2 reserved 0 when being read D1 CBIF Compare B interrupt flag 1 Cause of interrupt occurred 0 Cause of interrupt not occur...

Page 144: ... control circuit TOUTA5 TOUTB5 CAPA5 CAPB5 Interrupt request Compare B Capture B register T16A_CCB0 Compare A Capture A register T16A_CCA0 Counter block Ch 0 Comparator capture block Ch 0 Counter T16A_TC0 IOSC 0 1 2 3 1 0 OSC3 EXCL5 Divider 1 1 1 16384 CLKDIV T16A_CLK0 CLKEN T16A_CLK0 CLKSRC T16A_CLK0 OSC1 Divider 1 1 1 256 HCM TRMD PRESET PRUN T16A_CTL0 MULTIMD T16A_CLK0 Compare A signal Compare ...

Page 145: ... details are described later Notes The letter x in register names refers to a channel number 0 or 1 Example T16A_CTLx register Ch 0 T16A_CTL0 register Ch 1 T16A_CTL1 register The letter x in EXCLx CAPAx CAPBx TOUTAx and TOUTBx pins refers to a signal number Ch 0 5 Ch 1 6 Ch 0 EXCL5 CAPA5 CAPB5 TOUTA5 TOUTB5 Ch 1 EXCL6 CAPA6 CAPB6 TOUTA6 TOUTB6 T16a2 input Output Pins 13 2 Table 13 2 1 lists the in...

Page 146: ... an event counter or for measuring pulse widths by inputting an external clock or pulses The table below lists the external clock input pins It is not necessary to switch their pin functions from general purpose I O port However do not set the I O port to output mode 3 2 External Clock Input Pins Table 13 Channel external clock input pin T16A2 Ch 0 EXCL5 T16A2 Ch 1 EXCL6 internal clock division ra...

Page 147: ...values are matched The T16A_CCAx and T16A_ CCBx registers function as the compare A and compare B registers that are used for loading compare values in this mode When the counter reaches the value set in the compare A register during counting the comparator asserts the compare A signal At the same time the compare A interrupt flag is set and the interrupt signal of the timer channel is output to t...

Page 148: ...t cycles and pulse widths can be measured from the difference between two captured counter values read If the captured data is overwritten by the next trigger when the capture A or capture B interrupt flag has already been set the overwrite interrupt flag will be set This interrupt can be used to execute an overwrite error han dling To avoid occurrence of unnecessary overwrite interrupt the captur...

Page 149: ... Counter Selection Table 13 CCaBCnT 1 0 Counter channel 0x3 0x2 Reserved 0x1 Ch 1 Counter 1 0x0 Ch 0 Counter 0 Default 0x0 When using the T16A2 module in normal channel mode be sure to connect the counter block to the compara tor capture block in the same channel Counter block Ch 0 Comparator capture block Ch 0 Clock controller Ch 0 Counter block Ch 1 Comparator capture block Ch 1 Clock controller...

Page 150: ...be read Do not use the compare A interrupt in half clock mode Counter Control 13 5 Counter Reset 13 5 1 The counter can be reset to 0 by writing 1 to PRESET T16A_CTLx register Normally the counter should be reset by writing 1 to this bit before starting the count The counter is reset by the hardware if the counter reaches the compare B register value after the count starts Note Make sure the count...

Page 151: ...ion Timing in Comparator Mode Figure 13 Capture mode PRUN PRESET CAP A CAP B Count clock T16A_TCx T16A_CCAx T16A_CCBx when CAPATRG 1 0 0x1 CAPBTRG 1 0 0x3 Reset Capture A interrupt Capture B interrupt Capture B interrupt and capture B overwrite interrupt if CAPBIF 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 3 6 11 5 4 2 Operation Timing in Capture Mode Figure 13 Timer Output Control 13 6 The timer that has ...

Page 152: ... by the compare A and compare B signals 6 2 TOUT Generation Mode Table 13 TOuTaMD 1 0 TOuTBMD 1 0 When compare a occurs When compare B occurs 0x3 No change Toggle 0x2 Toggle No change 0x1 Rise Fall 0x0 Disable output Default 0x0 TOUTAMD 1 0 and TOUTBMD 1 0 are also used to turn the TOUT outputs On and Off TOuT signal polarity selection By default an active High output signal is generated This logi...

Page 153: ...2 2n 1 2n 0 1 1 2 n 1 n 0 1 1 2 3 4 2n 4 2n 3 2n 2 2n 1 n T16A_CCBx Count clock T16A_TCx Dual edge counter TOUTAx TOUTBx Example HCM 1 T16A_CCAx 1 and T16A_CCBx 5 When TOUTAMD 1 0 TOUTBMD 1 0 0x1 and TOUTAINV TOUTBINV 0 5 10 0 0 1 2 3 4 7 8 9 10 0 1 1 2 4 5 0 1 5 6 3 6 4 PWM Waveform Output Timings in Half Clock Mode Figure 13 T16a2 interrupts 13 7 The T16A2 module can generate the following six k...

Page 154: ...quests for this cause is not sent to the ITC Capture a overwrite interrupt This interrupt request is generated if the capture A register is overwritten by a new external trigger when the capture A interrupt flag CAPAIF has been set a counter value has already been loaded to the capture A register It sets the interrupt flag CAPAOWIF T16A_IFLGx register in the T16A2 module to 1 To use this interrupt...

Page 155: ...h 1 Data Register Counter data 0x5424 T16A_CCCTL1 T16A Comparator Capture Ch 1 Control Register Controls the comparator capture block and TOUT 0x5426 T16A_CCA1 T16A Compare Capture Ch 1 A Data Register Compare A capture A data 0x5428 T16A_CCB1 T16A Compare Capture Ch 1 B Data Register Compare B capture B data 0x542a T16A_IEN1 T16A Compare Capture Ch 1 Interrupt Enable Register Enables disables int...

Page 156: ... the count clock supply the clock to the EXCLx pin D1 MULTIMD Multi Comparator Capture Mode Select Bit T16A_CLK0 register Sets the T16A2 module to multi comparator capture mode 1 R W Multi comparator capture mode 0 R W Normal channel mode default In multi comparator capture mode the clock for Ch 0 configured in the T16A_CLK0 register is sup plied to all timer channels In normal channel mode differ...

Page 157: ... T16A2 generates a compare A signal when the T16A_TCx register value matches the T16A_CCAx register Notes T16A2 must be placed into comparator mode to set half clock mode as it is effective only when PWM waveform is generated Be sure to set T16A2 to normal clock mode under a condition shown below 1 When T16A2 is placed into capture mode 2 When TOUTAMD T16A_CCCTLx register is set to 0x2 or 0x3 3 Wh...

Page 158: ...0 when read out default Writing 1 to this bit resets the counter to 0 Note Make sure the counter is halted CLKEN T16A_CLKx register 0 before setting PRESET D0 PRUN Counter Run Stop Control Bit Starts stops the count 1 W Run 0 W Stop 1 R Counting 0 R Stopped default The counter starts counting when PRUN is written as 1 and stops when written as 0 The counter data is retained even if the counter is ...

Page 159: ...ger Select Bits Selects the trigger edge s of the external signal CAPBx at which the counter value is captured in the capture B register 8 5 Capture B Trigger Edge Selection Table 13 CaPBTRG 1 0 Trigger edge 0x3 Falling edge and rising edge 0x2 Falling edge 0x1 Rising edge 0x0 Not triggered Default 0x0 CAPBTRG 1 0 are control bits for capture mode and are ineffective in comparator mode D 13 12 TOU...

Page 160: ...al waveform TOUTAx output is changed by the compare A and compare B signals These bits are also used to turn the TOUT A output On and Off 8 8 TOUT A Generation Mode Table 13 TOuTaMD 1 0 When compare a occurs When compare B occurs 0x3 No change Toggle 0x2 Toggle No change 0x1 Rise Fall 0x0 Disable output Default 0x0 TOUTAMD 1 0 are control bits for comparator mode and are ineffective in capture mod...

Page 161: ...408 0x5428 16 bits D15 0 CCB 15 0 Compare capture B data CCB15 MSB CCB0 LSB 0x0 to 0xffff 0x0 R W D 15 0 CCB 15 0 Compare Capture B Data Bits In comparator mode CCBMD T16A_CCCTLx register 0 Sets a compare B data which will be compared with the counter value through this register The counter value comparison timing varies according to the CBUFEN T16A_CTLx register value For more information see Com...

Page 162: ...ts D1 CBIE Compare B Interrupt Enable Bit Enables or disables compare B interrupts 1 R W Interrupt enabled 0 R W Interrupt disabled default Setting CBIE to 1 enables compare B interrupt requests to the ITC Setting it to 0 disables interrupts D0 CAIE Compare A Interrupt Enable Bit Enables or disables compare A interrupts 1 R W Interrupt enabled 0 R W Interrupt disabled default Setting CAIE to 1 ena...

Page 163: ...register CAPBIF is reset by writing 1 D2 CAPAIF Capture A Interrupt Flag Bit Indicates whether the cause of capture A interrupt has occurred or not 1 R Cause of interrupt has occurred 0 R No cause of interrupt has occurred default 1 W Flag is reset 0 W Ignored CAPAIF is a T16A2 interrupt flag that is set to 1 when the counter value is captured in the capture A register CAPAIF is reset by writing 1...

Page 164: ...DUTY Duty match signal Comparator 1 1 T8OSC1 Module Configuration Figure 14 The 8 bit OSC1 timer includes an 8 bit up counter T8OSC1_CNT register an 8 bit compare data register T8OSC1_CMP register and an 8 bit PWM duty data register T8OSC1_DUTY register The up counter can be reset to 0 via software and counts up using the OSC1 division clock The count value can be read via software The compare dat...

Page 165: ...One shot mode These modes are selected using T8ORMD T8OSC1_CTL register Repeat mode T8ORMD 0 default Setting T8ORMD to 0 sets T8OSC1 to repeat mode In this mode once the count starts the timer continues running until stopped by the application program If the counter matches the compare data the timer resets the counter and continues counting The interrupt signal is output at the same time T8OSC1 s...

Page 166: ... Control 14 7 Make the following settings before starting T8OSC1 1 To output the PWM signal switch the output pin function to be used for T8OSC1 Refer to the I O Ports P chapter 2 Set the count mode one shot or repeat mode See Section 14 4 3 Select the count clock See Section 14 3 4 If using interrupts set the interrupt level and enable T8OSC1 interrupts See Section 14 9 5 Reset the counter See Se...

Page 167: ...r see Section 14 6 and the duty ratio can be adjusted by the PWM duty data register The timer outputs a low level signal until the counter value matches the value of the PWM duty data register When the counter value exceeds the value of the PWM duty data the output pin changes to high Once the counter counts up to the compare data register value the counter is reset and the output pin returns to l...

Page 168: ...T8OIE Control Register Details 14 10 10 1 List of T8OSC1 Registers Table 14 address Register name Function 0x5065 OSC_T8OSC1 T8OSC1 Clock Control Register Controls the count clock 0x50c0 T8OSC1_CTL T8OSC1 Control Register Sets the timer mode and starts stops the timer 0x50c1 T8OSC1_CNT T8OSC1 Counter Data Register Counter data 0x50c2 T8OSC1_CMP T8OSC1 Compare Data Register Sets compare data 0x50c3...

Page 169: ... Reserved D4 T8ORST Timer Reset Bit Resets the timer 1 W Reset 0 W Ignored 0 R Always 0 when being read default Writing 1 to this bit resets the counter to 0 D 3 2 Reserved D1 T8ORMD Count Mode Select Bit Selects the count mode 1 R W One shot mode 0 R W Repeat mode default Setting T8ORMD to 0 sets T8OSC1 to repeat mode In this mode once the count starts the timer con tinues to run until stopped by...

Page 170: ...mpare Data Register T8OSC1_CMP Register name address Bit name Function Setting init R W Remarks T8OSC1 Compare Data Register T8OSC1_CMP 0x50c2 8 bits D7 0 T8OCMP 7 0 Compare data T8OCMP7 MSB T8OCMP0 LSB 0x0 to 0xff 0x0 R W D 7 0 T8OCMP 7 0 Compare Data Sets compare data Default 0x0 The data set is compared against the counter data and a compare match interrupt cause is generated if the contents ma...

Page 171: ... 1 Notes To prevent interrupt recurrences the T8OSC1 module interrupt flag T8OIF must be reset in the interrupt handler routine following a T8OSC1 interrupt To prevent generating unnecessary interrupts reset T8OIF before enabling compare match interrupts using T8OIE T8OSC1 PWM Duty Data Register T8OSC1_DUTY Register name address Bit name Function Setting init R W Remarks T8OSC1 PWM Duty Data Regis...

Page 172: ...n erate interrupts using the 32 Hz 8 Hz 2 Hz and 1 Hz signals This clock timer is normally used for various timing functions such as a clock Operation Clock 15 2 The CT module uses the 256 Hz clock output by the CLG module as the operation clock The CLG module gener ates this operation clock by dividing the OSC1 clock into 1 128 resulting in a frequency of 256 Hz when the OSC1 clock frequency is 3...

Page 173: ...etained for CTRUN reading until the timer actually stops Figure 15 4 2 shows the Run Stop control timing chart CTRUN WR CT_CNT register 0x57 0x58 0x59 0x5a 0x5b 0x5c CTRUN RD 256 Hz 4 2 Run Stop Control Timing Chart Figure 15 Executing the slp instruction while the timer is running CTRUN 1 will destabilize the timer operation during restarting from SLEEP status When switching to SLEEP status stop ...

Page 174: ...0x5003 CT_IFLG Clock Timer Interrupt Flag Register Indicates resets interrupt occurrence status The CT registers are described in detail below These are 8 bit registers Note When data is written to the registers the Reserved bits must always be written as 0 and not 1 Clock Timer Control Register CT_CTL Register name address Bit name Function Setting init R W Remarks Clock Timer Control Register CT...

Page 175: ...l falling edge while setting to 0 disables interrupts D 7 4 Reserved D3 CTIE32 32 Hz Interrupt Enable Bit Enables or disables 32 Hz interrupts 1 R W Interrupt enabled 0 R W Interrupt disabled default D2 CTIE8 8 Hz Interrupt Enable Bit Enables or disables 8 Hz interrupts 1 R W Interrupt enabled 0 R W Interrupt disabled default D1 CTIE2 2 Hz Interrupt Enable Bit Enables or disables 2 Hz interrupts 1...

Page 176: ... Hz interrupt has occurred or not 1 R Cause of interrupt has occurred 0 R No cause of interrupt has occurred default 1 W Flag is reset 0 W Ignored D1 CTIF2 2 Hz Interrupt Flag Bit Indicates whether the cause of 2 Hz interrupt has occurred or not 1 R Cause of interrupt has occurred 0 R No cause of interrupt has occurred default 1 W Flag is reset 0 W Ignored D0 CTIF1 1 Hz Interrupt Flag Bit Indicate...

Page 177: ...lock and allows count data to be read out by software The SWT module can also generate interrupts using the 100 Hz approximately 100 Hz 10 Hz approximately 10 Hz and 1 Hz signals Operation Clock 16 2 The SWT module uses the 256 Hz clock output by the CLG module as the operation clock The CLG module generates this operation clock by dividing the OSC1 clock into 1 128 resulting in a frequency of 256...

Page 178: ...ing at 2 256 second and 3 256 second intervals The 1 10 second counter counts the approximate 10 Hz signal generated by the 1 100 second counter at a ra tio of 4 6 and generates a 1 Hz signal Count up will be pseudo 1 10 second counting at 25 256 second and 26 256 second intervals Timer Reset 16 4 Reset the SWT module by writing 1 to SWTRST SWT_CTL register This clears the counter to 0 Apart from ...

Page 179: ...le includes functions for generating the following three kinds of interrupts 100 Hz 10 Hz and 1 Hz interrupts The SWT module outputs a single interrupt signal shared by the above three interrupt causes to the interrupt control ler ITC The interrupt flag in the SWT module should be read to identify the cause of interrupt that occurred 100 hz 10 hz 1 hz interrupts The 100 Hz approximate 100 Hz 10 Hz...

Page 180: ...gister SWT_CTL 0x5020 8 bits D7 5 reserved 0 when being read D4 SWTRST Stopwatch timer reset 1 Reset 0 Ignored 0 W D3 1 reserved D0 SWTRUN Stopwatch timer run stop control 1 Run 0 Stop 0 R W D 7 5 Reserved D4 SWTRST Stopwatch Timer Reset Bit Resets the SWT module 1 W Reset 0 W Ignored 0 R Always 0 when read default Writing 1 to this bit resets the counter to 0x0 When reset in Run state the timer r...

Page 181: ...led 0 R W Interrupt disabled default D0 SIE100 100 Hz Interrupt Enable Bit Enables or disables 100 Hz interrupts 1 R W Interrupt enabled 0 R W Interrupt disabled default Stopwatch Timer Interrupt Flag Register SWT_IFLG Register name address Bit name Function Setting init R W Remarks Stopwatch Timer Interrupt Flag Register SWT_IFLG 0x5023 8 bits D7 3 reserved 0 when being read D2 SIF1 1 Hz interrup...

Page 182: ...C17624 604 622 602 621 Technical Manual D0 SIF100 100 Hz Interrupt Flag Bit Indicates whether the cause of 100 Hz interrupt has occurred or not 1 R Cause of interrupt has occurred 0 R No cause of interrupt has occurred default 1 W Flag is reset 0 W Ignored ...

Page 183: ... Hz clock output by the CLG module as the operation clock The CLG module generates this operation clock by dividing the OSC1 clock into 1 128 resulting in a frequency of 256 Hz when the OSC1 clock frequency is 32 768 kHz The frequency described in this chapter will vary accordingly for other OSC1 clock frequencies The CLG module does not include a 256 Hz clock output control bit The 256 Hz clock i...

Page 184: ...ore executing the halt instruction Reset WDT before resuming operations after HALT mode is cleared SleeP mode The clock supplied from the CLG module is stopped in SLEEP mode which also stops WDT To prevent generation of an unnecessary NMI or reset after clearing SLEEP mode reset WDT before executing the slp instruction WDT should also be stopped as required using WDTRUN 3 0 Control Register Detail...

Page 185: ...read D1 WDTMD NMI Reset mode select 1 Reset 0 NMI 0 R W D0 WDTST NMI status 1 NMI occurred 0 Not occurred 0 R D 7 2 Reserved D1 WDTMD NMI Reset Mode Select Bit Selects NMI or reset generation on counter overflow 1 R W Reset 0 R W NMI default Setting this bit to 1 outputs a reset signal when the counter overflows Setting to 0 outputs an NMI sig nal D0 WDTST NMI Status Bit Indicates a counter overfl...

Page 186: ...udes a 2 byte receive data buffer and a 1 byte transmit data buffer Includes an RZI modulator demodulator circuit to support IrDA 1 0 compatible infrared communications Can detect parity error framing error and overrun error during receiving Can generate receive buffer full transmit buffer empty and receive error interrupts Figure 18 1 1 shows the UART configuration Shift register Receive data buf...

Page 187: ...XEN UART_CTLx register 0 before altering SSCK internal clock Setting SSCK to 0 default selects the internal clock UART Ch 0 uses the T8F Ch 0 output clock as the trans fer clock while UART Ch 1 uses the T8F Ch 1 output clock Thus T8F must be programmed to output a clock suited to the transfer rate For more information on T8F control see the Fine Mode 8 bit Timers T8F chapter external clock Setting...

Page 188: ... D7 s2 s1 D0 D1 D2 D3 D4 D5 D6 D7 p s2 s1 D0 D1 D2 D3 D4 D5 D6 D7 s2 s3 s1 D0 D1 D2 D3 D4 D5 D6 D7 p s2 s3 s1 start bit s2 s3 stop bit p parity bit Figure 18 4 1 Transfer Data Format Data Transfer Control 18 5 Make the following settings before starting data transfers 1 Select the input clock See Section 18 3 Program T8F to output the transfer clock 2 Set the transfer data format See Section 18 4 ...

Page 189: ...eiver circuit is activated by setting RXEN to 1 enabling data to be received from an external serial de vice When the external serial device sends a start bit the receiver circuit detects its Low level and starts sampling the following data bits The data bits are sampled at the sampling clock rising edge and the lead bit is loaded into the receive shift register as LSB Once the MSB has been receiv...

Page 190: ...it S2 Stop bit P Parity bit Rd Data read from RXD 7 0 5 2 Data Receiving Timing Chart Figure 18 Disabling data transfers After a data transfer is completed both transmission and reception write 0 to RXEN to disable data transfers The data being transferred cannot be guaranteed if RXEN is set to 0 while data is being sent or received Before setting RXEN to 0 check the data transfer status with soft...

Page 191: ...s empty by load ing the transmit data written to it to the shift register while TIEN is 1 an interrupt request is sent to the ITC An interrupt occurs if other interrupt conditions are met If TIEN is set to 0 default interrupt requests for this cause will not be sent to the ITC You can inspect the TDBE flag in the UART interrupt handler routine to determine whether the UART interrupt is attributabl...

Page 192: ...ator input shift register output Modulator output SOUTx S1 D0 D1 D2 D3 D4 D5 D6 D7 P S2 S3 S1 Start bit S2 S3 Stop bits P Parity bit 8 1 Transmission Signal Waveform Figure 18 The received IrDA signal is input to the demodulator circuit and the Low pulse width is converted to 16 sclk16 cycles before entry to the receive shift register The demodulator circuit uses the pulse detection clock selected...

Page 193: ...transfer 0x4105 UART_EXP0 UART Ch 0 Expansion Register Sets IrDA mode 0x4120 UART_ST1 UART Ch 1 Status Register Indicates transfer buffer and error statuses 0x4121 UART_TXD1 UART Ch 1 Transmit Data Register Transmit data 0x4122 UART_RXD1 UART Ch 1 Receive Data Register Receive data 0x4123 UART_MOD1 UART Ch 1 Mode Register Sets transfer data format 0x4124 UART_CTL1 UART Ch 1 Control Register Contro...

Page 194: ...e data buffer is full when data is received in the shift register The receive data buffer is not overwritten even if this error occurs The shift register is overwritten as soon as the error occurs OER is reset by writing 1 D3 RD2B Second Byte Receive Flag Bit Indicates that the receive data buffer contains two received data 1 R Second byte can be read 0 R Second byte not received default RD2B is s...

Page 195: ...ta in the buf fer is read out first D 7 0 RXD 7 0 Receive Data Data in the receive data buffer is read out in sequence starting with the oldest Received data is placed in the receive data buffer The receive data buffer is a 2 byte FIFO that allows proper data reception until it fills even if data is not read out If the buffer is full and the shift register also contains received data an overrun er...

Page 196: ...e input clock 1 R W External clock SCLKx 0 R W Internal clock default Select whether the internal clock T8F output clock or an external clock input via SCLKx pin is used Writing 1 to SSCK selects an external clock Writing 0 to it selects the internal clock UART Ch x Control Registers UART_CTLx Register name address Bit name Function Setting init R W Remarks UART Ch x Control Register UART_CTLx 0x4...

Page 197: ... Enable Bit Enables data transfer by the UART 1 R W Enabled 0 R W Disabled default Set RXEN to 1 before starting UART transfers Setting RXEN to 0 disables data transfers The data being transferred cannot be guaranteed if RXEN is set to 0 while data is being sent or received Before setting RXEN to 0 check the data transfer status with software in consideration of the communication procedure The dat...

Page 198: ...f at least 2 IrDA receive detection clock cycles as valid Select an appropriate clock to enable detection of input pulses with a minimum width of 1 41 µs D 3 1 Reserved D0 IRMD IrDA Mode Select Bit Switches the IrDA interface function on and off 1 R W On 0 R W Off default Set IRMD to 1 to use the IrDA interface When IRMD is set to 0 this module functions as a normal UART with no IrDA functions ...

Page 199: ...the SPI module configuration Shift register Receive data buffer 1 byte SDIx PCLK Internal bus ITC SPI Ch x Bus I F and control registers SPICLKx SPISSx Shift register Transmit data buffer 1 byte Clock transfer control SDOx T16 Ch 1 output clock Interrupt control 1 4 1 1 SPI Module Configuration Figure 19 Notes In the S1C17602 621 the transmit buffer empty interrupt can only be used in master mode ...

Page 200: ...K to 1 selects the T16 Ch 1 output clock setting to 0 selects the PCLK 4 clock Using the T16 Ch 1 output clock enables programmable transfer rates For more information on T16 control see the 16 bit Timers T16 chapter PCLK 16 bit timer Ch 1 output clock or PCLK 4 SPI clock SPICLKx output 3 1 Master Mode SPI Clock Figure 19 In slave mode the SPI clock is input via the SPICLKx pin Data Transfer Condi...

Page 201: ... from the SPICLKx pin The data in the shift register is shifted in sequence at the clock rising or falling edge as determined by CPHA SPI_CTLx register and CPOL SPI_CTLx register see Figure 19 4 1 and sent from the SDOx pin The SPI module includes two status flags for transfer control SPTBE SPI_STx register and SPBSY SPI_STx register The SPTBE flag indicates the transmit data buffer status This fl...

Page 202: ...t the rising or falling edge of the clock determined by CPHA SPI_CTLx register and CPOL SPI_CTLx register See Figure 19 4 1 The received data is loaded into the receive data buffer once the 8 bits of data are received in the shift register The received data in the buffer can be read from SPRDB 7 0 SPI_RXDx register The SPI module includes SPRBF SPI_STx register for reception control The SPRBF flag...

Page 203: ...this interrupt set SPTIE SPI_CTLx register to 1 If SPTIE is set to 0 default interrupt requests for this cause will not be sent to the ITC When transmit data written to the transmit data buffer is transferred to the shift register the SPI module sets SPTBE SPI_STx register to 1 indicating that the transmit data buffer is empty If transmit buffer empty inter rupts are enabled SPTIE 1 an interrupt r...

Page 204: ...hen being read D2 SPBSY Transfer busy flag master 1 Busy 0 Idle 0 R ss signal low flag slave 1 ss L 0 ss H D1 SPRBF Receive data buffer full flag 1 Full 0 Not full 0 R D0 SPTBE Transmit data buffer empty flag 1 Empty 0 Not empty 1 R D 15 3 Reserved D2 SPBSY Transfer Busy Flag Bit Master Mode ss Signal Low Flag Bit Slave Mode Master mode Indicates the SPI transfer status 1 R Operating 0 R Standby d...

Page 205: ... Remarks SPI Ch x Receive Data Register SPI_RXDx 0x4324 16 bits D15 8 reserved 0 when being read D7 0 SPRDB 7 0 SPI receive data buffer SPRDB7 MSB SPRDB0 LSB 0x0 to 0xff 0x0 R D 15 8 Reserved D 7 0 SPRDB 7 0 SPI Receive Data Buffer Bits Contains the received data Default 0x0 SPRBF SPI_STx register is set to 1 data full as soon as data is received and the shift register data has been transferred to...

Page 206: ...les SPI transmit data buffer empty interrupts 1 R W Enabled 0 R W Disabled default Setting SPTIE to 1 enables the output of SPI interrupt requests to the ITC due to a transmit data buffer empty These interrupt requests are generated when the data written to the transmit data buffer is trans ferred to the shift register when transmission starts SPI interrupts are not generated by transmit data buff...

Page 207: ...elects slave mode Master mode performs data transfer with the internal clock In slave mode data is transferred by inputting the clock from the master device D0 SPEN SPI Enable Bit Enables or disables SPI module operation 1 R W Enabled 0 R W Disabled default Setting SPEN to 1 starts the SPI module operation enabling data transfer Setting SPEN to 0 stops the SPI module operation Note The SPEN bit sh...

Page 208: ...e reliability of data transfers Can generate transmit buffer empty and receive buffer full interrupts Figure 20 1 1 shows the I2CM configuration Shift register SDA0 SDA SCL SCL0 I2C master clock from T16 Ch 2 Internal bus ITC I2C master Bus I F and control registers Shift register Clock transfer control Noise filter Interrupt control 1 1 I2CM Module Configuration Figure 20 i2CM input Output Pins 2...

Page 209: ...t used for synchronization clock input Settings Before Data Transfer 20 4 The I2CM module includes an optional noise filter function that can be selected via the application program noise filter function The I2CM module includes a function for filtering noise from the SDA0 and SCL0 pin input signals This function is enabled by setting NSERM I2CM_CTL register to 1 Note that using this function requ...

Page 210: ...pecifying Slave Address and Transfer Direction Figure 20 The transfer direction bit indicates the data transfer direction after the slave address has been sent This is set to 0 when sending data from the master to the slave and to 1 when receiving data from the slave To send a slave address set the address with the transfer direction bit to RTDT 7 0 I2CM_DAT register At the same time set TXE I2CM_...

Page 211: ...e clock from the SCL0 pin with the SDA line at high impedance The data is shifted into the shift register from the MSB first in sync with the clock RXE is reset to 0 when D7 is loaded The received data is loaded to RTDT 7 0 once the 8 bit data has been received in the shift register The I2CM module includes two status bits for receive control RBRDY I2CM_DAT register and RBUSY I2CM_CTL register The...

Page 212: ...AK transfer has finished and the time for the slave device to finish clock stretching has elapsed STP is reset to 0 when the stop condition is generated Continuing data transfer Generating Repeated start condition To make it possible to continue with a different data transfer after data transfer completion the I2C master this module can generate a repeated start condition SDA0 output SCL0 output R...

Page 213: ... Receiving end Receiving start PCLK T16 Ch 2 output SCL0 SDA0 RXE RBUSY RTACK RTDT 7 0 RBRDY Interrupt D 7 0 D7 D6 ACK D0 5 8 Data Receiving Figure 20 PCLK T16 Ch 2 output SCL0 SDA0 STP STP setting Stop condition I2C bus free 5 9 Stop Condition Generation Figure 20 i2CM interrupts 20 6 The I2CM module includes a function for generating the following two different types of interrupts Transmit buffe...

Page 214: ...ull interrupt can be cleared by reading data from RTDT 7 0 I2CM_DAT regis ter Note After an I2CM interrupt occurs determine whether a transmit buffer empty interrupt or a receive buffer full interrupt has occurred according to the I2C master transmit receive processing being executed at that time Note that it cannot be checked using a register For more information on interrupt processing see the I...

Page 215: ...lter function on or off 1 R W On 0 R W Off default The I2CM module includes a function for filtering noise from the SDA0 and SCL0 pin input signals This function is enabled by setting NSERM to 1 Note that using this function requires setting the I2CM clock T16 Ch 2 output clock frequency to 1 6 or less of PCLK D 3 2 Reserved D1 STP Stop Control Bit Generates the stop condition 1 R W Stop condition...

Page 216: ...S1C17624 604 622 the RBRDY flag can be used to await reception with polling Ac cess the I2CM_DAT register in 16 bit size to read both RBRDY and RTDT 7 0 at a time and use the RTDT 7 0 value as valid receive data when RBRDY 1 D10 RXE Receive Execution Bit Receives 1 byte of data 1 R W Data reception start 0 R W Ineffective default Setting RXE to 1 and TXE to 0 starts receiving for 1 byte of data RX...

Page 217: ... is received before this register is read out the contents are overwritten by the most recent received data Serial data input from the SDA0 pin with MSB lead ing is converted to parallel with the High level bit set to 1 and the Low level bit set to 0 then loaded to this register I2C Master Interrupt Control Register I2CM_ICTL Register name address Bit name Function Setting init R W Remarks I2C Mas...

Page 218: ...y receive buffer full and bus status interrupts Figure 21 1 1 shows the I2CS configuration SCL1 BFR Shift register SDA1 SDA SCL Internal bus ITC I2C Slave Bus I F and control registers Shift register Clock transfer control Noise filter Interrupt control 1 1 I2CS Module Configuration Figure 21 Note The I2CS module does not support general call address and 10 bit address mode i2CS input Output Pins ...

Page 219: ...4 Reset 21 4 1 The I2CS module must be reset to initialize the communication process and to set the I2C bus into free status high impedance The following shows two methods for resetting the module 1 Software reset The I2CS module can be reset using SOFTRESET I2CS_CTL register To reset the I2CS module write 1 to SOFTRESET to place the I2CS module into reset status then write 0 to SOFTRESET to relea...

Page 220: ...s provided to detect the I2C slave address sent from the master in this status The asynchronous address detection function in this module is disabled by default When using the asynchro nous address detection function set ASDET_EN I2CS_CTL register to 1 If the slave address sent from the master has matched with one that has been set in this I2CS module when the asynchronous address detection functi...

Page 221: ...I2C slave device BUSY is maintained at 1 until a stop condition is detected SELECTED is maintained at 1 until a stop condition or repeated start condition is de tected The value of the transfer direction bit is set to R W I2CS_ASTAT register so use R W to select the transmit or receive handling If the slave address of this module is detected when the asynchronous address detection function has bee...

Page 222: ...XUDF is set to 1 so an error handling should be performed in the interrupt han dler routine TXUDF is cleared by writing 1 When the clock stretch function is enabled When the clock stretch function has been enabled the I2CS module pulls down the SCL1 pin to low to gen erate a clock stretch wait status until transmit data is written to the I2CS_TRNS register Transmit data bits are output from the SD...

Page 223: ...les of the I2C clock SCL1 input clock from RXRDY being set to 1 When the clock stretch function is enabled When the clock stretch function has been enabled the I2CS module pulls down the SCL1 pin to low to gen erate a clock stretch wait status until the received data is read from the I2CS_RECV register If the next data has been received without reading the received data RDATA 7 0 will be overwritt...

Page 224: ...a transfer Always make sure that BUSY and SELECTED are 0 before disabling data transfer To deactivate the I2CS module set I2CSEN I2CS_CTL register to 0 Timing charts PCLK SCL1 input SCL1 output SDA1 input SDA1 output R W BUSY SELECTED TXEMP TXUDF DA_NAK DA_STOP Transmit data shift register SDATA 7 0 Interrupt A6 H L valid D 7 0 A5 A4 A3 A2 A1 A0 D7 D6 ACK Start condition Slave address reception Da...

Page 225: ... three different types of interrupts Transmit interrupt Receive interrupt Bus status interrupt The I2CS module outputs one interrupt signal shared by the three above interrupt causes to the interrupt controller ITC Transmit interrupt When the transmit data written to SDATA 7 0 I2CS_TRNS register is sent to the shift register TXEMP I2CS_ ASTAT register is set to 1 and an interrupt signal is output ...

Page 226: ...ition above 5 RXOVF I2CS_STAT register This bit is set to 1 when the next data has been received before the received data is read the received data is overwritten When the clock stretch function is disabled 6 BFREQ I2CS_STAT register This bit is set to 1 when a bus free request is accepted 7 DA_STOP I2CS_STAT register This bit is set to 1 if a stop condition or a repeated start condition is de tec...

Page 227: ... 1 When the clock stretch function is enabled The master device is placed into wait status by the clock stretch function so transmit data can be written after TXEMP is set However if the previous transmit data is still stored in SDATA 7 0 it will be sent immediately after TXEMP has been set In order to avoid this problem clear the I2CS_ TRNS register using TBUF_CLR I2CS_CTL register before this mo...

Page 228: ... necessary to insert a waiting time be tween writing 1 and 0 If a new transmission is started when the I2CS_TRNS register still stores data for the previous trans mission that has already finished the data will be sent when TXEMP I2CS_ASTAT register is set In order to avoid this problem clear the I2CS_TRNS register using TBUF_CLR before starting transmis sion before slave selection The clear opera...

Page 229: ... starting data communication D2 NF_EN Noise Filter On Off Bit Turns the noise filter on or off 1 R W On 0 R W Off default The I2CS module contains a function to remove noise from the SDA1 and SCL1 input signals This function is enabled by setting NF_EN to 1 D1 ASDET_EN Async Address Detection On Off Bit Turns the asynchronous address detection function on or off 1 R W On 0 R W Off default The I2CS...

Page 230: ...5 8 Reserved D7 BSTAT Bus Status Transition Bit Indicates transition of the bus status 1 R Changed 0 R Unchanged default When one of the TXUDF RXOVF BFREQ DMS ASDET DA_NAK and DA_STOP bits is set to 1 BSTAT is also set to 1 and an interrupt signal is output to the ITC if the interrupt is enabled with BSTAT_IEN I2CS_ICTL register This interrupt can be used to perform an error or terminate handling ...

Page 231: ...t value of this IC and the SDA line status When SELECTED I2CS_ASTAT register is set to 0 you can ignore DMS without a problem even if it is set to 1 as there is a difference in the response code ACK NAK from the selected slave device When the I2CS module is placed into asynchronous address detection mode ASDET_EN 1 a DMS does not occur as in the condition above D2 ASDET Async Address Detection Sta...

Page 232: ...al is output to the ITC if the interrupt is enabled with RXRDY_IEN I2CS_ICTL register This interrupt can be used to read the received data from the I2CS_RECV register After RXRDY is set to 1 it is reset to 0 when the I2CS_RECV register is read D3 TXEMP Transmit Data Empty Bit Indicates that transmit data can be written 1 R Transmit data empty data can be written 0 R Transmit data still stored data...

Page 233: ...R W Disabled default When BSTAT_IEN is set to 1 I2C bus status interrupt requests to the ITC are enabled A bus status in terrupt request occurs when BSTAT I2CS_STAT register is set to 1 See description of BSTAT When BSTAT_IEN is set to 0 a bus status interrupt will not be generated D1 RXRDY_IEN Receive Interrupt Enable Bit Enables or disables the I2CS receive interrupt 1 R W Enabled 0 R W Disabled...

Page 234: ...e 22 1 1 shows the configuration of the REMC module Carrier generator Internal bus IR remote controller Bus I F and control registers Data length counter REMO REMI Edge detector Modulator Interrupt control PCLK CLG Divider 1 1 1 16K ITC 1 1 REMC Module Configuration Figure 22 ReMC input Output Pins 22 2 Table 22 2 1 lists the REMC input output pins 2 1 List of REMC Pins Table 22 Pin name i O Qty F...

Page 235: ...ngth s cg_clk REMCL 1 Carrier L section length s cg_clk REMCH Carrier H section length data value REMCL Carrier L section length data value cg_clk Carrier generation clock frequency The carrier signal is generated from these settings as shown in Figure 22 3 1 Example CGCLK 3 0 0x2 PCLK 4 REMCH 5 0 2 REMCL 5 0 1 PCLK Carrier generation clock Count Carrier 0 1 2 0 1 0 Carrier H section length Carrie...

Page 236: ...ta length fits within this range Data Transfer Control 22 5 Make the following settings before starting data transfers 1 Configure the carrier signal See Section 22 3 2 Select the data length counter clock See Section 22 4 3 Set the interrupt conditions See Section 22 6 Note Make sure the REMC module is halted REMEN REMC_CFG register 0 before changing the above settings Data transmission control R...

Page 237: ... Step 4 in the interrupt handler routine executed by the data length counter underflow 6 Terminating data transmission To terminate data transmission set REMEN to 0 after the final data transmission has completed after an under flow interrupt has occurred Data reception control PCLK Data length counter clock REMI input REMDT Sampled waveform REMRIF REMFIF Interrupt signal REMLEN 7 0 Write 0xff x 2...

Page 238: ...ngth counter has counted down to 0 this interrupt cause sets the interrupt flag RE MUIF REMC_INT register inside the REMC to 1 When data is being transmitted the underflow interrupt indicates that the specified data length has been trans mitted When receiving data the underflow interrupt indicates that data has been received or a receive error has occurred To use this interrupt set REMUIE REMC_INT...

Page 239: ...ock and data transfer 0x5342 REMC_CAR REMC Carrier Length Setup Register Sets the carrier H L section lengths 0x5344 REMC_LCNT REMC Length Counter Register Sets the transmit receive data length 0x5346 REMC_INT REMC Interrupt Control Register Controls interrupts The REMC registers are described in detail below These are 16 bit registers Note When data is written to the registers the Reserved bits m...

Page 240: ...ations REMC Carrier Length Setup Register REMC_CAR Register name address Bit name Function Setting init R W Remarks REMC Carrier Length Setup Register REMC_CAR 0x5342 16 bits D15 14 reserved 0 when being read D13 8 REMCL 5 0 Carrier L length setup 0x0 to 0x3f 0x0 R W D7 6 reserved 0 when being read D5 0 REMCH 5 0 Carrier H length setup 0x0 to 0x3f 0x0 R W D 15 14 Reserved D 13 8 REMCL 5 0 Carrier ...

Page 241: ...x0 The counter stops when it reaches 0 and generates a cause of underflow interrupt For data transmission Set the transmit data length for data transmission When a value corresponding to the data pulse width is written the data length counter starts counting down from that value The counter stops counting and generates a cause of underflow interrupt when it reaches 0 Set the subsequent transmit da...

Page 242: ... to identify the cause of interrupt occurred If the interrupt enable bit is set to 0 the interrupt is disabled Notes To prevent interrupt recurrences the REMC module interrupt flag must be reset in the inter rupt handler routine after an REMC interrupt has occurred To prevent generating unnecessary interrupts reset the interrupt flag before enabling inter rupts by the interrupt enable bit D 15 11 ...

Page 243: ...RIE Rising Edge Interrupt Enable Bit Enables or disables input signal rising edge interrupts 1 R W Interrupt enabled 0 R W Interrupt disabled default D0 REMUIE Underflow Interrupt Enable Bit Enables or disables data length counter underflow interrupts 1 R W Interrupt enabled 0 R W Interrupt disabled default ...

Page 244: ...verted display mode COM and SEG pins Supports inverting memory bit assignment to the COM and SEG pins LCD contrast adjustment Selectable from among 16 values Other functions LFRO signal output frame interrupt Figure 23 1 1 shows the LCD driver and drive power supply configuration COMx SEGx LFRO LCLK OSC1 HSCLK Divider 1 32 1 512 Gate LC 3 0 DSPAR DSPC 1 0 LDUTY 2 0 FRMCNT 1 0 DSPREV SEGREV COMREV ...

Page 245: ...ce use LCKDV 2 0 OSC_LCLK register to select the division ratio 3 1 1 HSCLK Division Ratio Selection Table 23 lCKDV 2 0 Division ratio 0x7 0x5 Reserved 0x4 1 512 0x3 1 256 0x2 1 128 0x1 1 64 0x0 1 32 Default 0x0 Clock enable The LCLK supply is enabled with LCKEN OSC_LCLK register The LCKEN default setting is 0 which stops the clock Setting LCKEN to 1 feeds the clock generated as above to the LCD d...

Page 246: ...SCLK LCKDV 512 fHSCLK LCKDV 680 fHSCLK LCKDV 1024 Default setting fHSCLK HSCLK IOSC or OSC3 clock frequency LCKDV HSCLK division ratio 1 32 to 1 512 The frame signal generated can be output to an external device via the LFRO pin To output the frame signal set LFROUT LCD_CCTL register to 1 However the output pin must be switched for LFRO output using the port function select bit as the pin is confi...

Page 247: ... COM0 to COM3 SEG0 to SEG39 160 segments 0x2 1 3 COM0 to COM2 SEG0 to SEG39 120 segments 0x1 1 2 COM0 to COM1 SEG0 to SEG39 80 segments 0x0 Static COM0 SEG0 to SEG39 40 segments Default 0x4 The COM4 SEG39 to COM7 SEG36 pins are configured to COM pins when 1 8 duty is selected or SEG pins when other duty is selected The drive bias is fixed at 1 3 three potentials VC1 VC2 VC3 for all duty settings D...

Page 248: ...C2 VC1 VSS COM2 VC3 VC2 VC1 VSS COM3 VC3 VC2 VC1 VSS COM4 VC3 VC2 VC1 VSS COM5 VC3 VC2 VC1 VSS COM0 1 2 3 4 5 6 7 SEGx COM6 VC3 VC2 VC1 VSS COM7 SEGx VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS 1 frame Frame interrupt Frame interrupt LCD display status Off On 4 2 1 1 8 Duty Drive Waveform Figure 23 ...

Page 249: ...OM0 COM1 VDD VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS COM2 VC3 VC2 VC1 VSS COM3 VC3 VC2 VC1 VSS COM0 1 2 3 SEGx VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS SEGx 1 frame Frame interrupt Frame interrupt LCD display status Off On 4 2 2 1 4 Duty Drive Waveform Figure 23 ...

Page 250: ... 2 LFRO COM0 COM1 VDD VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS COM2 VC3 VC2 VC1 VSS COM0 1 2 SEGx VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS SEGx 1 frame Frame interrupt Frame interrupt LCD display status Off On 4 2 3 1 3 Duty Drive Waveform Figure 23 ...

Page 251: ... VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS SEGx 1 frame Frame interrupt Frame interrupt LCD display status Off On 4 2 4 1 2 Duty Drive Waveform Figure 23 0 0 LFRO COM0 1 frame Frame interrupt Frame interrupt LCD display status VDD VSS VC3 VC2 VC1 VSS COM0 SEGx VC3 VC2 VC1 VSS VC3 VC2 VC1 VSS Off On SEGx 4 2 5 Static Drive Waveform Figure 23 ...

Page 252: ...n 1 4 1 3 1 2 duty or static drive is selected When 1 4 1 3 1 2 duty or static drive is selected two screen areas can be reserved within the display memory and DSPAR LCD_DCTL register can be used to switch between the screens Setting DSPAR to 0 selects dis play area 0 setting to 1 selects display area 1 SeG pin assignment The display memory address assignment for the SEG pins can be inverted using...

Page 253: ...3ff D0 Display area 0 DSPAR 0 Unavailable area COM0 COM2 D1 COM1 COM1 D2 COM2 COM0 D3 Unused area general purpose memory D4 Display area 1 DSPAR 1 COM0 COM2 D5 COM1 COM1 D6 COM2 COM0 D7 Unused area general purpose memory SEGREV 1 SEG0 SEG55 SEGREV 0 SEG55 SEG0 5 3 S1C17624 622 Display Memory Map 1 3 duty Figure 23 Bit Address COMREV 1 COMREV 0 0x53c0 0x53f7 0x53f8 0x53ff D0 Display area 0 DSPAR 0 ...

Page 254: ...1 COMREV 0 0x53c0 0x53e3 0x53e4 0x53e7 0x53e8 0x53ff D0 Display area Unused area general purpose memory Unavailable area COM0 COM7 D1 COM1 COM6 D2 COM2 COM5 D3 COM3 COM4 D4 COM4 COM3 D5 COM5 COM2 D6 COM6 COM1 D7 COM7 COM0 SEGREV 1 SEG0 SEG35 SEGREV 0 SEG35 SEG0 5 6 S1C17604 602 621 Display Memory Map 1 8 duty Figure 23 Bit Address COMREV 1 COMREV 0 0x53c0 0x53e7 0x53e8 0x53ff D0 Display area 0 DSP...

Page 255: ...OMREV 1 COMREV 0 0x53c0 0x53e7 0x53e8 0x53ff D0 Display area 0 DSPAR 0 Unavailable area COM0 COM1 D1 COM1 COM0 D2 Unused area general purpose memory D3 D4 Display area 1 DSPAR 1 COM0 COM1 D5 COM1 COM0 D6 Unused area general purpose memory D7 SEGREV 1 SEG0 SEG39 SEGREV 0 SEG39 SEG0 5 9 S1C17604 602 621 Display Memory Map 1 2 duty Figure 23 Bit Address COMREV 1 COMREV 0 0x53c0 0x53e7 0x53e8 0x53ff D...

Page 256: ...ring the display memory DSPC 1 0 is reset to 0x0 Display off after an initial reset DSPC 1 0 is also reset to 0x0 when the slp instruction is executed and it reverts to the previous setting after SLEEP mode is canceled lCD Contrast adjustment 23 6 2 The LCD contrast can be adjusted to one of 16 levels using LC 3 0 LCD_CADJ register Contrast is adjusted by controlling the voltages VC1 to VC3 output...

Page 257: ...23 address Register name Function 0x5063 OSC_LCLK LCD Clock Select Register Selects the LCD clock 0x50a0 LCD_DCTL LCD Display Control Register Controls the LCD display 0x50a1 LCD_CADJ LCD Contrast Adjustment Register Controls the contrast 0x50a2 LCD_CCTL LCD Clock Control Register Controls the LCD drive duty 0x50a3 LCD_VREG LCD Voltage Regulator Control Register Controls the LCD drive voltage regu...

Page 258: ...gnment control 1 Normal 0 Reverse 1 R W D6 COMREV Common output assignment control 1 Normal 0 Reverse 1 R W D5 DSPAR Display memory area control 1 Area 1 0 Area 0 0 R W D4 DSPREV Reverse display control 1 Normal 0 Reverse 1 R W D3 2 reserved 0 when being read D1 0 DSPC 1 0 LCD display control DSPC 1 0 Display 0x0 R W 0x3 0x2 0x1 0x0 All off All on Normal display Display off D7 SEGREV Segment Outpu...

Page 259: ...D system voltage regulator stops and the VC1 to VC3 pins are all set to VSS level Since All on and All off directly control the driving waveform output by the LCD driver display memory data is not altered COM pins are set to dynamic drive for All on and to static drive for All off This function can be used to make the display flash on and off without altering the display memo ry DSPC 1 0 is reset ...

Page 260: ...Hz 1 504 48 12 Hz 1 681 32 5 Hz 1 1008 1 2 duty 0x1 128 Hz 1 256 64 Hz 1 512 48 19 Hz 1 680 32 Hz 1 1024 Static 0x0 128 Hz 1 256 64 Hz 1 512 48 19 Hz 1 680 32 Hz 1 1024 Default setting When the clock source is HSCLK 8 6 Frame Frequency Settings Table 23 Drive duty lDuTY 2 0 setting FRMCnT 1 0 setting 0x0 0x1 0x2 0x3 1 8 duty 0x4 fHSCLK LCKDV 256 fHSCLK LCKDV 512 fHSCLK LCKDV 680 fHSCLK LCKDV 1024 ...

Page 261: ...n mode 1 On 0 Off 0 R W D3 1 reserved 0 when being read D0 VCSEL VC reference voltage select 1 VC2 0 VC1 0 R W For more information on the control bit see LCD Voltage Regulator Control Register LCD_VREG in the Power Supply chapter LCD Interrupt Mask Register LCD_IMSK Register name address Bit name Function Setting init R W Remarks LCD Interrupt Mask Register LCD_IMSK 0x50a5 8 bits D7 1 reserved 0 ...

Page 262: ... conversion mode for single channel or multi channels Continuous conversion mode for single channel or multi channels terminated with software Supports three conversion triggers Software trigger External trigger input from the ADTRG pin T16 Ch 0 underflow trigger The conversion results can be read as 16 bit data with the 10 bit converted data aligned to left or right Two types of interrupts can be...

Page 263: ...Ports P chapter a D Converter Settings 24 3 Make the following settings before starting A D conversion 1 Set the analog input pins See Section 24 2 2 Set the A D conversion clock 3 Select the A D conversion start and end channels 4 Select the A D conversion mode 5 Select the A D conversion trigger source 6 Set the sampling time 7 Select the conversion result storing mode 8 When using A D converter...

Page 264: ...ADCE 2 0 ADC10_TRG register respectively 3 2 1 Relationship between ADCS ADCE and Input Channels Table 24 aDCS 2 0 aDCe 2 0 Channel selected 0x7 AIN7 0x6 AIN6 0x5 AIN5 0x4 AIN4 0x3 AIN3 0x2 AIN2 0x1 AIN1 0x0 AIN0 Default 0x0 Example Operation of one A D conversion ADCS 2 0 0 ADCE 2 0 0 Converted only in AIN0 ADCS 2 0 0 ADCE 2 0 3 Converted in the following order AIN0 AIN1 AIN2 AIN3 ADCS 2 0 2 ADCE...

Page 265: ...using an external trigger to start A D conversion ensure to maintain the Low period of the trigger signal input to the ADTRG pin for two or more S1C17 Core operating clock cycles 2 16 bit timer T16 Ch 0 The underflow signal of T16 Ch 0 is used as a trigger Since the T16 underflow cycle can be programmed with flexibility this trigger source is effective when periodic A D conversions are required Fo...

Page 266: ...y mode STMD 0 0 0 MSB 10 bit conversion results LSB 3 6 1 Conversion Data Alignment Figure 24 a D Conversion Control and Operations 24 4 The A D converter should be controlled in the sequence shown below 1 Activate the A D converter 2 Start A D conversion 3 Read the A D conversion results 4 Terminate A D conversion activating a D Converter 24 4 1 After the settings described in Section 24 3 have b...

Page 267: ...are read from ADD 15 0 ADOWE should be read to check whether the read data is valid or not Or enable conversion data overwrite error interrupts and perform error han dling using the interrupt Once ADOWE is set it will not be reset until software writes 1 Since ADCF is also set simultaneously with ADOWE read out the converted data to reset ADCF Note Occurrence of an overwrite error does not stop co...

Page 268: ...version Sampling Conversion AIN0 invalid 3 Single channel AIN0 continuous conversion mode ADCS 0 ADCE 0 ADMS 1 ADEN Trigger ADIBS A D operation ADD 15 0 ADCF Conversion result read ADOWE Interrupt request AIN0 Ch 0 Ch 1 Ch 0 AIN0 Sampling Conversion AIN1 AIN1 Sampling Clear Clear Conversion AIN0 converted data AIN1 converted data 0 is written to ADCTL to stop conversion Sampling Conversion AIN0 in...

Page 269: ...ADC10 interrupt handler routine to determine whether the ADC10 interrupt is attributable to an overwrite error If ADOWE is 1 perform error handling by the interrupt handler routine The interrupt cause ADOWE is reset to 0 by writing 1 For more information on interrupt processing see the Interrupt Controller ITC chapter Notes To prevent interrupt recurrences the ADCF ADC10_CTL register and ADOWE ADC...

Page 270: ...D 15 14 Reserved D 13 11 ADCE 2 0 End Channel Select Bits Sets the conversion end channel with a channel number from 0 to 7 Default 0x0 AIN0 Analog inputs can be A D converted continuously from the channel set by ADCS 2 0 to the channel set by ADCE 2 0 in one A D conversion If only one channel is to be A D converted set the same channel number in both ADCS 2 0 and ADCE 2 0 6 2 Relationship between...

Page 271: ...4 aDST 2 0 Sampling time in a D conversion clock cycles 0x7 9 cycles 0x6 8 cycles 0x5 7 cycles 0x4 6 cycles 0x3 5 cycles 0x2 4 cycles 0x1 3 cycles 0x0 2 cycles Default 0x7 A D Control Status Register ADC10_CTL Register name address Bit name Function Setting init R W Remarks A D Control Status Register ADC10_CTL 0x5384 16 bits D15 reserved 0 when being read D14 12 ADICH 2 0 Conversion channel indic...

Page 272: ... D8 ADCF Conversion Completion Flag Bit Indicates that A D conversion has been completed 1 R Conversion completed cause of interrupt has occurred 0 R Being converted standby cause of interrupt has not occurred default ADCF is set to 1 when A D conversion is completed and the converted data is loaded into ADD 15 0 ADC10_ADD register ADCF is a cause of ADC10 interrupt When ADCF is set to 1 a convers...

Page 273: ... enables the A D converter meaning it is ready to start A D conversion i e ready to accept a trigger When ADEN is 0 the A D converter is disabled meaning it is unable to accept a trigger However set ting ADEN to 0 does not stop A D conversion being currently executed To stop A D conversion write 0 to ADCTL Before setting the modes start end channels or other A D converter conditions be sure to res...

Page 274: ...DDF 3 0 Division ratio 0xf Reserved 0xe 1 32768 0xd 1 16384 0xc 1 8192 0xb 1 4096 0xa 1 2048 0x9 1 1024 0x8 1 512 0x7 1 256 0x6 1 128 0x5 1 64 0x4 1 32 0x3 1 16 0x2 1 8 0x1 1 4 0x0 1 2 Default 0x0 Note To use the A D converter the clock used in the A D converter must be supplied by turning on the peripheral module clock PCLK output from the clock generator CLG ...

Page 275: ...terrupt Figure 25 1 1 shows the RFC configuration To ITC RFCLK RFCLKO SENB0 SENA0 REF0 RFIN0 RFIN1 REF1 SENA1 SENB1 Multi plexer Ch 0 oscillator circuit Counter control circuit Ch 1 oscillator circuit CR oscillation control circuit Measurement counter MC 23 0 Internal data bus HSCLK OSC1 Divider 1 1 1 8 RFC Time base counter TC 23 0 Interrupt control circuit Gate TCCLK 1 1 R F Converter Configurat...

Page 276: ...cludes a clock source selector dividers and a gate circuit for controlling the operation clock Note The operation clock TCCLK must be enabled before setting the R F converter Otherwise the R F converter cannot operate normally Clock source selection Use RFTCKSRC OSC_RFC register to select the clock source from HSCLK IOSC or OSC3 and OSC1 Set ting RFTCKSRC to 1 default selects OSC1 and setting it t...

Page 277: ...0x0 DC oscillation mode for measuring resistive sensors Default 0x0 DC oscillation mode for measuring resistive sensors SMODe 1 0 0x0 default This mode drives the oscillator with the reference resistor and resistive sensor by applying DC bias voltage Select this mode when a DC bias resistive sensor is connected This mode enables two resistive sensors to be connected to a channel One reference resi...

Page 278: ...put For the threshold voltage of the Schmitt input buffer see Electrical Characteristics Setting EVTEN RFC_CTL register to 1 enables this function The measurement control procedure is the same as that when the internal oscillator circuit is used SENBx SENAx REFx RFINx Supports rectangular waves triangular waves and sign waves 4 2 1 External Clock Input Figure 25 The unused pins should be left open...

Page 279: ...h the same resistance ca pacitance will result Initial value Counter value at the end of sensor oscillation if no error introduced Setting a small initial value to the measurement counter improves measurement accuracy However the mea surement counter may overflow during sensor oscillation when the sensor value decreases below the reference element value the measurement will be canceled The initial...

Page 280: ...ly An interrupt can be generated at this point Read the time base counter value TC 23 0 X and store it to the memory by the interrupt handler routine When this interrupt is not used perform the same processing after checking if EREFIF has been set 6 2 The time base counter overflow sets OVTCIF to 1 indicating that the reference oscillation has been terminat ed abnormally An interrupt can be genera...

Page 281: ...interrupt handler routine When this interrupt is not used perform the same processing after checking if ESENAIF or ESENBIF has been set 6 2 The measurement counter overflow sets OVMCIF to 1 indicating that the sensor oscillation has been terminat ed abnormally An interrupt can be generated at this point Handle this error in the interrupt handler routine When this interrupt is not used perform the ...

Page 282: ... be sent to the ITC When the measurement counter overflows and a sensor oscillation is terminated abnormally the R F converter sets OVMCIF RFC_IFLG register to 1 If measurement counter overflow error interrupts are enabled OVMCIE 1 an interrupt request is sent simultaneously to the ITC Time base counter overflow error interrupt To use this interrupt set OVTCIE RFC_IMSK register to 1 If OVTCIE is s...

Page 283: ...1 Default 0x0 D1 RFTCKSRC RFC Clock Source Select Bit Selects the count clock source 1 R W OSC1 default 0 R W HSCLK IOSC or OSC3 D0 RFTCKEN RFC Clock Enable Bit Enables or disables the TCCLK clock supply 1 R W Enabled on 0 R W Disabled off default The RFTCKEN default setting is 0 which disables the clock supply Setting RFTCKEN to 1 sends the clock selected to the R F converter RFC Control Register...

Page 284: ...r Oscillation Mode Select Bits Selects an oscillation mode 8 3 Oscillation Mode Selection Table 25 SMODe 1 0 Oscillation mode 0x3 Reserved 0x2 DC oscillation mode for measuring capacitive sensors 0x1 AC oscillation mode for measuring resistive sensors 0x0 DC oscillation mode for measuring resistive sensors Default 0x0 For more information on the oscillation mode see Section 25 4 1 D 3 2 Reserved D...

Page 285: ...to SSENB does not start oscillation when SMODE 1 0 RFC_CTL register is 0x1 AC oscillation mode for resistive sensors or 0x2 DC oscillation mode for capacitive sensors When writing 1 to SREF SSENA or SSENB to start oscillation be sure to avoid that more than one bit are set to 1 Be sure to reset the interrupt flags in the RFC_IFLG register EREFIF ESENAIF ESENBIF OVMCIF and OVTCIF before starting os...

Page 286: ...pt enable 1 Enable 0 Disable 0 R W D3 OVMCIE MC overflow error interrupt enable 1 Enable 0 Disable 0 R W D2 ESENBIE Sensor B oscillation completion interrupt enable 1 Enable 0 Disable 0 R W D1 ESENAIE Sensor A oscillation completion interrupt enable 1 Enable 0 Disable 0 R W D0 EREFIE Reference oscillation completion interrupt enable 1 Enable 0 Disable 0 R W D 15 5 Reserved D4 OVTCIE TC Overflow Er...

Page 287: ...red 0 R No cause of interrupt has occurred default 1 W Flag is reset 0 W Ignored OVMCIF is set to 1 when a sensor oscillation is terminated abnormally due to measurement counter overflow OVMCIF is reset to 0 by writing 1 D2 ESENBIF Sensor B Oscillation Completion Interrupt Flag Bit Indicates the sensor B oscillation completion interrupt cause occurrence status 1 R Cause of interrupt has occurred 0...

Page 288: ...3 0 Clock enable Divider SVDCKEN Clock source selection SVDSRC SVDCLK HSCLK OSC1 1 512 Gate 1 1 SVD Configuration Figure 26 Operating Clock 26 2 The SVD module includes a clock source selector dividers and a gate circuit for controlling the operation clock Clock selection Use SVDSRC 1 0 OSC_SVD register to select the clock source from HSCLK IOSC or OSC3 and OSC1 Setting SVDSRC to 1 default selects...

Page 289: ...etection result becomes 1 This interrupt can be used to indicate bat tery depletion and to initiate the heavy load protection function See the following section for more information on interrupt control Note that if a temporary voltage drop causes an interrupt the interrupt will not be cleared even when the voltage subsequently returns to a value exceeding the comparison voltage The SVDDT should b...

Page 290: ...egister Enables disables interrupts 0x5104 SVD_IFLG SVD Interrupt Flag Register Indicates resets interrupt occurrence status The SVD module registers are described in detail below These are 8 bit registers Note When data is written to the registers the Reserved bits must always be written as 0 and not 1 SVD Clock Control Register OSC_SVD Register name address Bit name Function Setting init R W Rem...

Page 291: ...CMP Register name address Bit name Function Setting init R W Remarks SVD Comparison Voltage Register SVD_CMP 0x5101 8 bits D7 4 reserved 0 when being read D3 0 SVDC 3 0 SVD comparison voltage select SVDC 3 0 Voltage 0x0 R W 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 3 2 V 3 1 V 3 0 V 2 9 V 2 8 V 2 7 V 2 6 V 2 5 V 2 4 V 2 3 V 2 2 V 2 1 V 2 0 V 1 9 V 1 8 V reserved D 7 4 Reserve...

Page 292: ... Interrupt Mask Register SVD_IMSK 0x5103 8 bits D7 1 reserved 0 when being read D0 SVDIE SVD interrupt enable 1 Enable 0 Disable 0 R W D 7 1 Reserved D0 SVDIE SVD Interrupt Enable Bit Enables or disables interrupts when a power supply voltage drop is detected 1 R W Interrupt enabled 0 R W Interrupt disabled default Setting SVDIE to 1 enables SVD interrupt requests to the ITC setting to 0 disables ...

Page 293: ...pins DCLK DST2 DSIO are shared with I O ports and are initially set as the debug pins If the debugging function is not used these pins can be switched using the port function select bits to enable use as general purpose I O port pins For detailed information on pin function switching see the I O Ports P chapter Debug Break Operation Status 27 2 The S1C17 Core enters debug mode when the brk instruc...

Page 294: ...er Set instruction break address 4 Note that the debugger included in the S5U1C17001C Ver 1 2 1 or later is required to use five hardware PC breaks Control Register Details 27 4 4 1 List of Debug Registers Table 27 address Register name Function 0x4020 PSC_CTL Prescaler Control Register Controls prescalers 0x5322 MISC_OSC1 OSC1 Peripheral Control Register Enables peripheral operations in debug mod...

Page 295: ... 15 1 Reserved D0 O1DBG Run Stop Select Bit in Debug Mode except PCLK peripheral circuits Selects the operating status of the peripheral circuits that operate with a clock other than PCLK in debug mode 1 R W Run 0 R W Stop default Setting O1DBG to 1 enables the peripheral circuits that operate with a clock other than PCLK to run even in debug mode Setting it to 0 will stop them when the S1C17 Core...

Page 296: ...g Base Address Select Bit Selects the branching destination address when a debug interrupt occurs 1 R W 0x0 0 R W 0xfffc00 default D 7 3 Reserved D 2 0 IRAMSZ 2 0 IRAM Size Select Bits Selects the size of the internal RAM to be used 4 2 Internal RAM Size Selection Table 27 iRaMSZ 2 0 internal RaM size S1C17624 604 S1C17622 S1C17602 S1C17621 0x3 2KB 2KB Reserved Reserved 0x2 4KB 4KB Reserved defaul...

Page 297: ...the IBAR3 register are compared If they match an instruction break is generated If this bit is set to 0 no comparison is performed D5 IBE2 Instruction Break 2 Enable Bit Enables or disables instruction break 2 1 R W Enabled 0 R W Disabled default If this bit is set to 1 the instruction fetch address and the value set in the IBAR2 register are compared If they match an instruction break is generate...

Page 298: ... 2 Bits Sets instruction break address 2 Default 0x000000 Instruction Break Address Register 3 IBAR3 Register name address Bit name Function Setting init R W Remarks Instruction Break Address Register 3 IBAR3 0xffffbc 32 bits D31 24 reserved 0 when being read D23 0 IBAR3 23 0 Instruction break address 3 IBAR323 MSB IBAR30 LSB 0x0 to 0xffffff 0x0 R W D 31 24 Reserved D 23 0 IBAR3 23 0 Instruction B...

Page 299: ...ocessor output Flag output Operation result 1 1 Multiplier Divider Block Diagram Figure 28 Operation Mode and Output Mode 28 2 The Multiplier divider operates according to the operation mode specified by the application program As listed in Table 28 2 1 the multiplier divider supports nine operations The multiplication division and MAC results are 32 bit data therefore the S1C17 Core cannot read t...

Page 300: ...cation mode Performs unsigned multiplication 0x5 Signed multiplication mode Performs signed multiplication 0x6 Reserved 0x7 Signed MAC mode Performs signed MAC operation 0x8 Unsigned division mode Performs unsigned division 0x9 Signed division mode Performs signed division 0xa 0xf Reserved Multiplication 28 3 The multiplication function performs A 32 bits B 16 bits C 16 bits To perform a multiplic...

Page 301: ... operation mode to 0x8 unsigned division or 0x9 signed division Then send the 16 bit dividend B and 16 bit divisor C to the multiplier divider using a ld ca instruction The quotient and the residue will be stored in the low order 16 bits and the high order 16 bits of the operation result register respec tively The 16 bit quotient or residue according to the output mode specification and the flag s...

Page 302: ...ter Selector Argument 2 Argument 1 16 bits 32 bits Coprocessor output 16 bits Flag output 5 1 Data Path in Initialize Mode Figure 28 5 1 Initializing the Operation Result Register Table 28 Mode setting value instruction Operations Remarks 0x0 res 31 0 0x0 Setting the operating mode executes the initialization without sending data 0x1 ld cf rd rs res 31 16 0x0 res 15 0 rs ext imm9 ld cf rd imm7 res...

Page 303: ...odes operation result read mode and 16 high order bits output mode ld ca r1 r0 Loads the 16 high order bits of the result to r1 Conditions to set the overflow V flag An overflow occurs in a MAC operation and the overflow V flag is set to 1 when the signs of the multiplica tion result operation result register value and multiplication accumulation result match the following condi tions 5 3 Conditio...

Page 304: ...er into operation result read mode The operation result register keeps the loaded operation result until it is rewritten by other operation S1C17 Core Operation result register Selector Argument 2 Argument 1 Coprocessor output 16 bits Flag output 6 1 Data Path in Operation Result Read Mode Figure 28 6 1 Operation in Operation Result Read Mode Table 28 Mode setting value instruction Operations Flag...

Page 305: ...a 25 to 70 C Storage temperature Tstg 65 to 150 C Soldering temperature time Tsol 260 C 10 seconds lead section 1 In case of plastic package Recommended Operating Conditions 29 2 item Symbol Condition Min Typ Max unit Operating power supply voltage VDD Normal operation mode 1 8 3 6 V Flash programming mode 2 7 3 6 V Analog power supply voltage AVDD AVDD VDD 1 8 3 6 V Operating frequency fOSC3 Crys...

Page 306: ... OSC1 32kHz IOSC OFF OSC3 8MHz ceramic VD1MD 1 CPU OSC3 4500 6500 µA IEXE31 OSC1 32kHz IOSC ON OSC3 OFF VD1MD 1 CPU IOSC 1600 2400 µA Current consumption during execution in heavy load protection mode 1 IEXE1H OSC1 32kHz IOSC OFF OSC3 OFF CPU OSC1 HVLD 1 22 34 µA 1 The values of current consumption during execution were measured when a test program consisting of 60 5 ALU instructions 17 branch ins...

Page 307: ...sting of 60 5 ALU instructions 17 branch instructions 12 memory read instructions and 10 5 memory write instructions was executed continuously in the Flash memory Current consumption temperature characteristic in halT mode OSC1 operation OSC1 32 768kHz crystal IOSC OFF OSC3 OFF PCKEN 1 0 0x0 VD1MD 0 CCLKGR 1 0 0x0 Typ value 50 10 8 6 4 2 0 25 0 25 50 75 100 Ta C I HALT1 µA 50 10 8 6 4 2 0 25 0 25 ...

Page 308: ... OFF PCKEN 1 0 0x3 CCLKGR 1 0 0x0 Ta 25 C Typ value 0 0 6000 5000 4000 3000 2000 1000 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 fOSC3 MHz I EXE2 I EXE21 µA VD1MD 0 VD1MD 1 0 0 6000 5000 4000 3000 2000 1000 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 10 0 fOSC3 MHz I EXE2 I EXE21 µA VD1MD 0 VD1MD 1 S1C17624 604 622 S1C17602 621 Current consumption frequency characteristic during execution with OSC3 cloc...

Page 309: ...G1 25pF external CD1 built in Rf1 built in item Symbol Condition Min Typ Max unit Oscillation start time 1 tsta 3 s Built in drain capacitance CD1 In case of the chip 10 pF 1 Crystal resonator MC 146 manufactured by EPSON TOYOCOM R1 65kW Max CL 12 5pF OSC3 crystal oscillation Unless otherwise specified VDD 1 8 to 3 6V VSS 0V Ta 25 C RF3 1MW item Symbol Condition Min Typ Max unit Oscillation start ...

Page 310: ... pulse width 60 ns UART transfer rate RU 460800 bps UART transfer rate IrDA mode RUIrDA 115200 bps Input rise time tCR 80 ns Input fall time tCF 80 ns OSC3 clock cycle time tOSC3 125 ns OSC3 clock input duty tOSC3D 46 54 fSYS System operating clock frequency input Output Pin Characteristics 29 6 S1C17624 604 622 Unless otherwise specified VDD 1 8 to 3 6V VSS 0V Ta 25 to 70 C item Symbol Condition ...

Page 311: ...eshold voltage VT1 RESET 0 5VDD 0 9VDD V Low level Schmitt input threshold voltage VT1 RESET 0 1VDD 0 5VDD V High level Schmitt input threshold voltage 1 VT2 Pxx 0 5VDD 0 9VDD V Low level Schmitt input threshold voltage 1 VT2 Pxx 0 1VDD 0 5VDD V High level output current IOH Pxx VOH 0 9VDD 0 5 mA Low level output current IOL Pxx VOL 0 1VDD 0 5 mA Leakage current ILEAK Pxx RESET 1 1 µA Input pull u...

Page 312: ... CPOL 0 SPICLKx CPOL 1 SDIx SDOx tSPCK tSDO tSDH tSDS Master mode Unless otherwise specified VDD 1 8 to 3 6V VSS 0V Ta 25 to 70 C item Symbol Min Typ Max unit SPICLKx cycle time tSPCK 500 ns SDIx setup time tSDS 120 ns SDIx hold time tSDH 10 ns SDOx output delay time tSDO 20 ns Slave mode Unless otherwise specified VDD 1 8 to 3 6V VSS 0V Ta 25 to 70 C item Symbol Min Typ Max unit SPICLKx cycle tim...

Page 313: ...nnect 1MW load resistor between VSS and VC2 0 649 VC3 Typ 0 701 VC3 Typ V VC3 Connect 1MW load resistor between VSS and VC3 LC 3 0 0x0 Typ 0 96 2 56 Typ 1 04 V LC 3 0 0x1 2 62 V LC 3 0 0x2 2 68 V LC 3 0 0x3 2 74 V LC 3 0 0x4 2 80 V LC 3 0 0x5 2 86 V LC 3 0 0x6 2 92 V LC 3 0 0x7 2 98 V LC 3 0 0x8 3 04 V LC 3 0 0x9 3 10 V LC 3 0 0xa 3 15 V LC 3 0 0xb 3 21 V LC 3 0 0xc 3 27 V LC 3 0 0xd 3 33 V LC 3 0...

Page 314: ...o 3 6V VSS 0V Ta 25 to 70 C item Symbol Condition Min Typ Max unit Segment Common output current ISEGH SEGxx COMxx VSEGH VC3 0 1V 5 µA ISEGL SEGxx COMxx VSEGL 0 1V 5 µA S1C17624 604 622 lCD driver circuit current consumption Unless otherwise specified VDD 1 8 to 3 6V VSS 0V Ta 25 C C2 C5 0 1µF No LCD panel load PCKEN 1 0 0x0 OFF FLCYC 2 0 0x4 1 cycle CCLKGR 1 0 0x0 gear ratio 1 1 item Symbol Condi...

Page 315: ...oad lCD current consumption load characteristic When a load is connected to the VC3 pin only VDD 3 6V Ta 25 C Typ value 0 45 0 40 0 35 0 30 0 25 0 20 0 15 0 10 0 5 0 0 0 4 8 12 16 20 IVC3 µA I LCD1 I LCD2 µA VCSEL 0 VCSEL 1 a D Converter Characteristics 29 10 analog characteristics Unless otherwise specified VDD AVDD 1 8 to 3 6V VSS 0V Ta 25 to 70 C ADST 2 0 0x7 9 cycles item Symbol Condition Min ...

Page 316: ...ter clock frequency fTCCLK 8 2 MHz RFIN pin high level Schmitt input voltage VT 0 5 VDD 0 9 VDD V RFIN pin low level Schmitt input voltage VT 0 1 VDD 0 5 VDD V 1 The oscillation frequency IC deviation characteristic value may increase due to variations in oscillation frequency caused by leak age if the oscillation frequency is 1 kHz or lower 2 In these characteristics unevenness between production...

Page 317: ...ion in HALT mode or current consumption during execution when the R F converter is active Current consumption depends on the VDD voltage reference capacitance sensor capacitance and reference sensor oscilla tion frequency S1C17602 621 R F converter current consumption Unless otherwise specified VDD 3 6V VSS 0V Ta 25 C PCKEN 1 0 0x0 OFF CREF CSEN 1000pF RREF RSEN 100kW TCCLK 8MHz item Symbol Condit...

Page 318: ...VD voltage VSVD SVDC 3 0 0x0 V SVDC 3 0 0x1 Typ 0 96 1 8 Typ 1 04 V SVDC 3 0 0x2 1 9 V SVDC 3 0 0x3 2 0 V SVDC 3 0 0x4 2 1 V SVDC 3 0 0x5 2 2 V SVDC 3 0 0x6 2 3 V SVDC 3 0 0x7 2 4 V SVDC 3 0 0x8 2 5 V SVDC 3 0 0x9 2 6 V SVDC 3 0 0xa 2 7 V SVDC 3 0 0xb 2 8 V SVDC 3 0 0xc 2 9 V SVDC 3 0 0xd 3 0 V SVDC 3 0 0xe 3 1 V SVDC 3 0 0xf 3 2 V SVD circuit enable response time 1 tSVDEN 500 µs SVD circuit respo...

Page 319: ...se program count 2 CFEP 1000 times 1 Data transfer and data verification are included and erase program start control time is not included 2 The erase program count assumes that erasing programming or overwrite programming is one count and the programmed data is guaranteed to be retained for 10 years Flash memory current consumption Unless otherwise specified VDD 2 7 to 3 6V VD1MD 1 VSS 0V Ta 25 C...

Page 320: ...EXCL3 AIN5 P16 SCLK1 AIN4 P17 AIN3 P20 AIN2 P21 AIN1 P22 AIN0 P33 SCL1 SCL0 TOUTA6 CAPA6 P34 SDA1 SDA0 TOUTB6 CAPB6 P35 FOUT1 BFR P37 EXCL6 TOUTN3 LFRO TOUT4 P40 FOUTH P44 SCL1 P45 SDA1 P46 RFCLKO P47 EXCL5 TOUT4 P50 EXCL6 SCLK1 P51 SOUT1 TOUTA5 CAPA5 P52 SIN1 TOUTB5 CAPB5 P53 BFR P54 LFRO P55 TOUTA6 CAPA6 P56 TOUTB6 CAPB6 DSIO P41 DST2 P42 DCLK P43 P36 EXCL5 TOUT3 RFCLKO P00 REMO S1C17624 604 622...

Page 321: ... 128pin package Unit mm 65 96 33 64 INDEX 32 1 128 97 14 16 14 16 0 13min 0 23max 0 4 1 0 1 1 2 max 1 0 3min 0 75max 0 min 10 max 0 09min 0 2max TQFP14 100pin package Unit mm 51 75 26 50 INDEX 25 1 100 76 12 0 1 14 0 4 12 0 1 14 0 4 0 16 0 4 0 10 0 05 1 0 1 0 1 1 2 max 1 0 5 0 2 0 10 0 125 0 05 0 025 ...

Page 322: ...Manual VFBGa7h 144 package Top View Bottom View A1 Corner A1 Corner Index D S S e y E A A 1 ZD Z E φ φ b x M e N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 Symbol D E A A1 e b X y ZD ZE Min 0 26 Dimension in Millimeters Nom 7 7 0 23 0 5 0 5 0 5 Max 1 0 0 36 0 08 0 1 ...

Page 323: ...mer 0x4248 T16_INT1 T16 Ch 1 Interrupt Control Register Controls the interrupt 16 bit timer Ch 2 16 bit device 0x4260 T16_CLK2 T16 Ch 2 Count Clock Select Register Selects a count clock 0x4262 T16_TR2 T16 Ch 2 Reload Data Register Sets reload data 0x4264 T16_TC2 T16 Ch 2 Counter Data Register Counter data 0x4266 T16_CTL2 T16 Ch 2 Control Register Sets the timer mode and starts stops the timer 0x42...

Page 324: ...lock Control Register Ch 0 Controls the T16A2 Ch 0 clock S1C17624 604 0x5069 T16A_CLK1 T16A Clock Control Register Ch 1 Controls the T16A2 Ch 1 clock S1C17624 604 0x506e RTC_CC RTC Clock Control Register Controls the RTC clock source 0x5080 CLG_PCLK PCLK Control Register Controls the PCLK supply 0x5081 CLG_CCLK CCLK Control Register Configures the CCLK division ratio LCD driver 8 bit device 0x50a0...

Page 325: ...nable Register Enables P2 port inputs 0x5230 P3_IN P3 Port Input Data Register P3 port input data 0x5231 P3_OUT P3 Port Output Data Register P3 port output data 0x5232 P3_OEN P3 Port Output Enable Register Enables P3 port outputs 0x5233 P3_PU P3 Port Pull up Control Register Controls the P3 port pull up resistor 0x5234 P3_SM P3 Port Schmitt Trigger Control Register Controls the P3 port Schmitt tri...

Page 326: ...FC_MCH RFC Measurement Counter High Register 0x53a8 RFC_TCL RFC Time Base Counter Low Register Time base counter data 0x53aa RFC_TCH RFC Time Base Counter High Register 0x53ac RFC_IMSK RFC Interrupt Mask Register Enables disables interrupts 0x53ae RFC_IFLG RFC Interrupt Flag Register Indicates resets interrupt occurrence status 16 bit PWM timer T16A2 Ch 0 16 bit device S1C17624 604 0x5400 T16A_CTL...

Page 327: ... empty int enable 1 Enable 0 Disable 0 R W D3 2 reserved 0 when being read D1 RBFI Receive buffer full int condition setup 1 2 bytes 0 1 byte 0 R W D0 RXEN UART enable 1 Enable 0 Disable 0 R W UART Ch 0 Expansion Register UART_EXP0 0x4105 8 bits D7 reserved 0 when being read D6 4 IRCLK 2 0 IrDA receive detection clock division ratio select IRCLK 2 0 Division ratio 0x0 R W Source clock PCLK 0x7 0x6...

Page 328: ...0 16 bits D15 4 reserved 0 when being read D3 0 DF 3 0 Count clock division ratio select DF 3 0 Division ratio 0x0 R W Source clock PCLK 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reserved 1 16384 1 8192 1 4096 1 2048 1 1024 1 512 1 256 1 128 1 64 1 32 1 16 1 8 1 4 1 2 1 1 T8F Ch 0 Reload Data Register T8F_TR0 0x4202 16 bits D15 8 reserved 0 when being read D7 0 TR 7 0 Reload ...

Page 329: ...e width External clock Internal clock D7 5 reserved 0 when being read D4 TRMD Count mode select 1 One shot 0 Repeat 0 R W D3 2 reserved 0 when being read D1 PRESER Timer reset 1 Reset 0 Ignored 0 W D0 PRUN Timer run stop control 1 Run 0 Stop 0 R W T16 Ch 0 Interrupt Control Register T16_INT0 0x4228 16 bits D15 9 reserved 0 when being read D8 T16IE T16 interrupt enable 1 Enable 0 Disable 0 R W D7 1...

Page 330: ...its D15 4 reserved 0 when being read D3 0 DF 3 0 Count clock division ratio select DF 3 0 Division ratio 0x0 R W Source clock PCLK 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reserved 1 16384 1 8192 1 4096 1 2048 1 1024 1 512 1 256 1 128 1 64 1 32 1 16 1 8 1 4 1 2 1 1 T16 Ch 2 Reload Data Register T16_TR2 0x4262 16 bits D15 0 TR 15 0 Reload data TR15 MSB TR0 LSB 0x0 to 0xffff 0...

Page 331: ...eserved 0 when being read D0 T8FIF T8F interrupt flag 1 Cause of interrupt occurred 0 Cause of interrupt not occurred 0 R W Reset by writing 1 0x4306 0x4318 Interrupt Controller Register name address Bit name Function Setting init R W Remarks Interrupt Level Setup Register 0 ITC_LV0 0x4306 16 bits D15 11 reserved 0 when being read D10 8 ILV1 2 0 P1 interrupt level 0 to 7 0x0 R W D7 3 reserved 0 wh...

Page 332: ...eserved 0 when being read D7 0 SPRDB 7 0 SPI receive data buffer SPRDB7 MSB SPRDB0 LSB 0x0 to 0xff 0x0 R SPI Ch 0 Control Register SPI_CTL0 0x4326 16 bits D15 10 reserved 0 when being read D9 MCLK SPI clock source select 1 T16 Ch 1 0 PCLK 4 0 R W D8 MLSB LSB MSB first mode select 1 LSB 0 MSB 0 R W D7 6 reserved 0 when being read D5 SPRIE Receive data buffer full int enable 1 Enable 0 Disable 0 R W...

Page 333: ... Slave Access Status Register I2CS_ASTAT 0x436a 16 bits D15 5 reserved 0 when being read D4 RXRDY Receive data ready 1 Ready 0 Not ready 0 R D3 TXEMP Transmit data empty 1 Empty 0 Not empty 0 R D2 BUSY I2C bus status 1 Busy 0 Free 0 R D1 SELECTED I2C slave select status 1 Selected 0 Not selected 0 R D0 R W Read write direction 1 Output 0 Input 0 R I2C Slave Interrupt Control Register I2CS_ICTL 0x4...

Page 334: ...ister name address Bit name Function Setting init R W Remarks Clock Source Select Register OSC_SRC 0x5060 8 bits D7 2 reserved 0 when being read D1 HSCLKSEL High speed clock select 1 OSC3 0 IOSC 0 R W D0 CLKSRC System clock source select 1 OSC1 0 HSCLK 0 R W Oscillation Control Register OSC_CTL 0x5061 8 bits D7 6 IOSCWT 1 0 IOSC wait cycle select IOSCWT 1 0 Wait cycle 0x0 R W 0x3 0x2 0x1 0x0 8 cyc...

Page 335: ...024 1 680 1 512 1 256 D5 LFROUT LFRO output control 1 On 0 Off 0 R W D4 3 reserved 0 when being read D2 0 LDUTY 2 0 LCD duty select LDUTY 2 0 Duty 0x4 R W 0x7 0x5 0x4 0x3 0x2 0x1 0x0 reserved 1 8 1 4 1 3 1 2 Static LCD Voltage Regulator Control Register LCD_VREG 0x50a3 8 bits D7 5 reserved 0 when being read D4 LHVLD LCD heavy load protection mode 1 On 0 Off 0 R W D3 1 reserved 0 when being read D0...

Page 336: ... when being read D3 0 SVDC 3 0 SVD comparison voltage select SVDC 3 0 Voltage 0x0 R W 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 3 2 V 3 1 V 3 0 V 2 9 V 2 8 V 2 7 V 2 6 V 2 5 V 2 4 V 2 3 V 2 2 V 2 1 V 2 0 V 1 9 V 1 8 V reserved SVD Detection Result Register SVD_RSLT 0x5102 8 bits D7 1 reserved 0 when being read D0 SVDDT SVD detection result 1 Low 0 Normal R SVD Interrupt Mask ...

Page 337: ...TC Hour Register RTC_HOUR 0x5146 8 bits D7 reserved 0 when being read D6 RTCAP AM PM indicator 1 PM 0 AM X R W D5 4 RTCHH 1 0 RTC 10 hour counter 0 to 2 or 0 to 1 X R W D3 0 RTCHL 3 0 RTC 1 hour counter 0 to 9 X R W RTC Day Register RTC_DAY 0x5147 8 bits D7 6 reserved 0 when being read D5 4 RTCDH 1 0 RTC 10 day counter 0 to 3 X R W D3 0 RTCDL 3 0 RTC 1 day counter 0 to 9 X R W RTC Month Register R...

Page 338: ...y Entry Reset Configuration Register P0_KRST 0x5209 8 bits D7 2 reserved 0 when being read D1 0 P0KRST 1 0 P0 port key entry reset configuration P0KRST 1 0 Configuration 0x0 R W 0x3 0x2 0x1 0x0 P0 3 0 0 P0 2 0 0 P0 1 0 0 Disable P0 Port Input Enable Register P0_IEN 0x520a 8 bits D7 0 P0IEN 7 0 P0 7 0 port input enable 1 Enable 0 Disable 1 0xff R W P1 Port Input Data Register P1_IN 0x5210 8 bits D7...

Page 339: ... 1 0xff R W P2 Port Schmitt Trigger Control Register P2_SM 0x5224 8 bits D7 0 P2SM 7 0 P2 7 0 port Schmitt trigger input enable 1 Enable Schmitt 0 1 R Always enabled P2 Port Input Enable Register P2_IEN 0x522a 8 bits D7 0 P2IEN 7 0 P2 7 0 port input enable 1 Enable 0 Disable 1 0xff R W P3 Port Input Data Register P3_IN 0x5230 8 bits D7 0 P3IN 7 0 P3 7 0 port input data 1 1 H 0 0 L R P3 Port Output...

Page 340: ... port pull up enable 1 Enable 0 Disable 1 0x7f R W P5 Port Schmitt Trigger Control Register P5_SM S1C17624 622 0x5254 8 bits D7 reserved 0 when being read D6 3 P5SM 6 3 P5 6 3 port Schmitt trigger input enable 1 Enable Schmitt 0 1 R Always enabled D2 0 P5SM 2 0 P5 2 0 port Schmitt trigger input enable 1 Enable Schmitt 0 Disable CMOS 1 R W P5 Port Input Enable Register P5_IEN S1C17624 622 0x525a 8 ...

Page 341: ...7MUX 1 0 P17 port function select P17MUX 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved reserved AIN3 P17 D5 4 P16MUX 1 0 P16 port function select P16MUX 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved AIN4 SCLK1 P16 D3 2 P15MUX 1 0 P15 port function select P15MUX 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved AIN5 reserved P15 EXCL3 D1 0 P14MUX 1 0 P14 port function select P14MUX 1 0 Function 0x0 R W...

Page 342: ...A6 CAPA6 SCL0 SCL1 P33 D5 4 P32MUX 1 0 P32 port function select P32MUX 1 0 Function 0x0 R W TOUTB5 CAPB5 S1C17624 604 only 0x3 0x2 0x1 0x0 TOUTB5 CAPB5 SENB1 SDA0 P32 D3 2 P31MUX 1 0 P31 port function select P31MUX 1 0 Function 0x0 R W TOUTA5 CAPA5 S1C17624 604 only 0x3 0x2 0x1 0x0 TOUTA5 CAPA5 SENA1 SCL0 P31 D1 0 P30MUX 1 0 P30 port function select P30MUX 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 rese...

Page 343: ...ed reserved SDA1 P45 D1 0 P44MUX 1 0 P44 port function select P44MUX 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved reserved SCL1 P44 P5 3 0 Port Function Select Register P50_53PMUX S1C17624 622 0x52aa 8 bits D7 6 P53MUX 1 0 P53 port function select P53MUX 1 0 Function 0x0 R W 0x3 0x2 0x1 0x0 reserved reserved BFR P53 D5 4 P52MUX 1 0 P52 port function select P52MUX 1 0 Function 0x0 R W TOUTB5 CAPB5...

Page 344: ...3 0 Clock division ratio select T16EDF 3 0 Division ratio 0x0 R W Source clock PCLK 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reserved 1 16384 1 8192 1 4096 1 2048 1 1024 1 512 1 256 1 128 1 64 1 32 1 16 1 8 1 4 1 2 1 1 T16E Ch x Interrupt Mask Register T16E_IMSKx 0x530a 16 bits D15 2 reserved 0 when being read D1 CBIE Compare B interrupt enable 1 Enable 0 Disable 0 R W D0 CA...

Page 345: ...6 bits D15 9 reserved 0 when being read D8 DBADR Debug base address select 1 0x0 0 0xfffc00 0 R W D7 reserved 0 when being read D6 4 reserved 0x2 when being read D3 reserved 0 when being read D2 0 IRAMSZ 2 0 IRAM size select IRAMSZ 2 0 Size 0x2 R W 0x7 0x0 reserved IRAM Size Select Register MISC_IRAMSZ S1C17621 0x5326 16 bits D15 9 reserved 0 when being read D8 DBADR Debug base address select 1 0x...

Page 346: ... REMC_INT 0x5346 16 bits D15 11 reserved 0 when being read D10 REMFIF Falling edge interrupt flag 1 Cause of interrupt occurred 0 Cause of interrupt not occurred 0 R W Reset by writing 1 D9 REMRIF Rising edge interrupt flag 0 R W D8 REMUIF Underflow interrupt flag 0 R W D7 3 reserved 0 when being read D2 REMFIE Falling edge interrupt enable 1 Enable 0 Disable 0 R W D1 REMRIE Rising edge interrupt ...

Page 347: ...0 RFC clock division ratio select RFTCKDV 1 0 Division ratio 0x0 R W When the clock source is HSCLK 0x3 0x2 0x1 0x0 1 8 1 4 1 2 1 1 D1 RFTCKSRC RFC clock source select 1 OSC1 0 HSCLK 1 R W D0 RFTCKEN RFC clock enable 1 Enable 0 Disable 0 R W RFC Control Register RFC_CTL 0x53a0 16 bits D15 8 reserved 0 when being read D7 CONEN Continuous oscillation enable 1 Enable 0 Disable 0 R W D6 EVTEN Event co...

Page 348: ...0x5068 0x5400 0x540c 16 bit PWM Timer T16A2 Ch 0 S1C17624 604 Register name address Bit name Function Setting init R W Remarks T16A Clock Control Register Ch 0 T16A_CLK0 0x5068 8 bits D7 4 CLKDIV 3 0 Clock division ratio select CLKDIV 3 0 Division ratio 0x0 R W OSC3 or IOSC OSC1 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 1 16384 1 8192 1 4096 1 2048 1 1024 1 512 1 256 1 128 1 ...

Page 349: ...A_CCA0 0x5406 16 bits D15 0 CCA 15 0 Compare capture A data CCA15 MSB CCA0 LSB 0x0 to 0xffff 0x0 R W T16A Comparator Capture Ch 0 B Data Register T16A_CCB0 0x5408 16 bits D15 0 CCB 15 0 Compare capture B data CCB15 MSB CCB0 LSB 0x0 to 0xffff 0x0 R W T16A Comparator Capture Ch 0 Interrupt Enable Register T16A_IEN0 0x540a 16 bits D15 6 reserved 0 when being read D5 CAPBOWIE Capture B overwrite inter...

Page 350: ...unter reset 1 Reset 0 Ignored 0 W 0 when being read D0 PRUN Counter run stop control 1 Run 0 Stop 0 R W T16A Counter Ch 1 Data Register T16A_TC1 0x5422 16 bits D15 0 T16ATC 15 0 Counter data T16ATC15 MSB T16ATC0 LSB 0x0 to 0xffff 0x0 R T16A Comparator Capture Ch 1 Control Register T16A_CCCTL1 0x5424 16 bits D15 14 CAPBTRG 1 0 Capture B trigger select CAPBTRG 1 0 Trigger edge 0x0 R W 0x3 0x2 0x1 0x...

Page 351: ...IDIR 7 0 Processor ID 0x10 S1C17 Core 0x10 0x10 R Debug RAM Base Register DBRAM S1C17624 604 602 0xffff90 32 bits D31 24 Unused fixed at 0 0x0 0x0 R D23 0 DBRAM 23 0 Debug RAM base address S1C17624 604 0x1fc0 S1C17602 0x0fc0 R Debug Control Register DCR 0xffffa0 8 bits D7 IBE4 Instruction break 4 enable 1 Enable 0 Disable 0 R W D6 IBE3 Instruction break 3 enable 1 Enable 0 Disable 0 R W D5 IBE2 In...

Page 352: ...cessary oscillator circuits CLG module Operate the oscillator comprising the system clock source Where possible stop the other oscillators You can reduce current consumption by using OSC1 as the system clock and disable the IOSC and OSC3 oscillators CPu clock CClK Execute the halt instruction Execute the halt instruction when program execution by the CPU is not required for example when only the d...

Page 353: ...cute halt instruction 1 2 3 4 Oscillation system CLK Stop Run 1 1 Run Run Oscillation Oscillation system CLK Stop Run Run Execute halt instruction 1 2 3 4 Oscillation Oscillation system CLK Run low gear Run Run High Oscillation Oscillation system CLK Run 1 1 Run Run HALT and SLEEP mode cancelation methods CPU startup method 1 Startup by port Started up by an I O port or debug interrupt ICD forced ...

Page 354: ...supply voltage VDD is higher than 2 5 V Turning on the LCD voltage regulator heavy load protection will increase current consumption Turn off heavy load protection for normal operations Turn on only if the display is unstable If no LCD display is being used turn off the LCD driver Power supply voltage detection SVD circuit Operating the SVD circuit will increase current consumption Turn off power ...

Page 355: ...an 3 mm distance or located on other layers Avoid crossing wires 3 Use VSS to shield OSC1 OSC3 and OSC2 OSC4 pins and related wiring including wiring for adjacent circuit board layers Layers wired should be adequately shielded as shown to the right Fully ground adjacent lay ers where possible At minimum shield the area at least 5 mm around the above pins and wiring Even after implementing these pr...

Page 356: ...oise induced malfunctions Check the following three points if you suspect the presence of noise induced IC malfunctions 1 DSIO pin Low level noise to this pin will cause a switch to debug mode The switch to debug mode can be confirmed by the clock output from DCLK and a High signal from the DST2 pin For the product version we recommend connecting the DSIO pin directly to VDD or pulling up the DISO...

Page 357: ...of light for bare chip mounting The characteristics of semiconductor components can vary when exposed to light ICs may malfunction or non volatile memory data may be corrupted if ICs are exposed to light Consider the following precautions for circuit boards and products in which this IC is mounted to prevent IC malfunctions attributable to light exposure 1 Design and mount the product so that the ...

Page 358: ...es in the form of voltages exceeding the absolute maximum rating when mounting the product in addition to physical damage The following factors can give rise to these variations 1 Electromagnetically induced noise from industrial power supplies used in mounting reflow reworking after mounting and individual characteristic evaluation testing processes 2 Electromagnetically induced noise from a sold...

Page 359: ... t8f_0_1_handler 0x0c 0x30 T8F ch0 ch1 long t16_0_handler 0x0d 0x34 T16 ch0 long t16_1_handler 0x0e 0x38 T16 ch1 long t16_2_handler 0x0f 0x3c T16 ch2 long uart_0_handler 0x10 0x40 UART ch0 long i2cs_uart_1_handler 0x11 0x44 I2CS UART ch1 long spi_0_handler 0x12 0x48 SPI ch0 long i2cm_handler 0x13 0x4c I2CM long remc_handler 0x14 0x50 REMC long t16a2_1_handler 0x15 0x54 T16A2 ch1 long adc10_handler...

Page 360: ...tion is declared to locate the vector table in the vector section 2 Interrupt handler routine addresses are defined as vectors intXX_handler can be used for software interrupts 3 The program code is written in the text section 4 Sets the stack pointer 5 Sets the number of Flash controller access cycles Can be set to 1 cycle access for S1C17624 604 622 602 621 See the Memory Map chapter ...

Page 361: ...illation frequency Mhz Manufacturer Product number 1 0 Murata Manufacturing Co Ltd CSBLA1M00J58 B0 leaded Murata Manufacturing Co Ltd CSBFB1M00J58 R1 SMD 2 0 Murata Manufacturing Co Ltd CSTCC2M00G56 R0 SMD 4 0 Murata Manufacturing Co Ltd CSTLS4M00G56 B0 leaded Murata Manufacturing Co Ltd CSTCR4M00G55 R0 SMD 8 0 Murata Manufacturing Co Ltd CSTLS8M00G56 B0 leaded Murata Manufacturing Co Ltd CSTCE8M0...

Page 362: ...ufacturer Product number 4 0 Murata Manufacturing Co Ltd CSTCR4M00G53 R0 SMD Murata Manufacturing Co Ltd CSTCR4M00G53095 R0 SMD Murata Manufacturing Co Ltd CSTLS4M00G53095 B0 leaded 8 0 Murata Manufacturing Co Ltd CSTLS8M00G53095 B0 leaded Note Please ask the manufacturer to evaluate the resonator mounted on the circuit board 4 CG3 CD3 RD3 RF3 recommended values name Frequency Mhz Product number C...

Page 363: ...tput Modified Figures 7 7 2 and 7 7 3 7 14 7 15 CLG PCLK Control Register CLG_PCLK Old No description New Peripheral modules that use PCLK Interrupt controller ITC Notes The interrupt controller ITC needs PCLK only when the register is set 9 5 9 11 P I O port chattering filter function Old No description New Notes An unexpected interrupt may occur disabled before placing the CPU into SLEEP status ...

Page 364: ...e Make sure that SPEN is set to 1 before writing data to start data transmission reception 20 2 I2CM I2C connection example Added Figure 20 2 1 I2CM Synchronization clock upper limit of transfer rate Old No description New When the I2CM module is used to 50 kbps in standard mode or 200 kbps in fast mode 20 3 I2CM Transmit data specifying slave address and transfer direction Modified Figure 20 5 2 ...

Page 365: ...next start condition New Indicates that a stop condition or a repeated start condition is detected I2CS module sets DA_STOP to 1 At the same time it initializes the I2C communication process I2CS I2C Slave Access Status Register I2CS_ASTAT D1 SELECTED I2C Slave Select Status Bit Old After SELECTED is set to 1 it is reset to 0 when a stop condition is detected New After SELECTED is set to 1 it is r...

Page 366: ...0 S1C17624 604 AP E 1 Recommended resonators Recommended resonators for S1C17624 604 622 4 CG3 CD3 RD3 RF3 recommended values Modified the table AP E 2 Recommended resonators Recommended resonators for S1C17602 621 Old No description New 4 CG3 CD3 RD3 RF3 recommended values The values enclosed with are the built in capacitances of the resonator 411914902 3 6 IRAM Size Select Register MISC_IRAMSZ O...

Page 367: ...or a built in ROM model 12 6 T16E Precautions Old No description New 4 Be sure to set T16EDF 3 0 T16E_DFx register to 0x0 PCLK 1 1 when using fine mode 13 15 T16A2 T16A Counter Ch x Control Registers T16A_CTLx D3 CBUFEN Compare Buffer Enable Bit Old Note Make sure the counter is halted PRUN 0 before setting PRESET New Note Make sure the counter is halted CLKEN T16A_CLKx register 0 before setting P...

Page 368: ...057 CHINA Phone 86 755 2699 3828 Fax 86 755 2699 3838 EPSON HONG KONG LTD Unit 715 723 7 F Trade Square 681 Cheung Sha Wan Road Kowloon Hong Kong Phone 852 2585 4600 Fax 852 2827 4346 EPSON TAIWAN TECHNOLOGY TRADING LTD 14F No 7 Song Ren Road Taipei 110 TAIWAN Phone 886 2 8786 6688 Fax 886 2 8786 6660 EPSON SINGAPORE PTE LTD 1 HarbourFront Place 03 02 HarbourFront Tower One Singapore 098633 Phone ...

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