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6 FUNCTIONS

S1C17 CORE MANUAL

Seiko Epson Corporation

6-11

(Rev. 1.2)

6.5 Debug Circuit

The S1C17 Core has a debug circuit to assist in software development by the user.

6.5.1 Debugging Functions

The debug circuit provides the following functions:

• Instruction break

A debug interrupt is generated before the set instruction address is executed. An instruction break can be set at
two addresses.

• Single step

A debug interrupt is generated every instruction executed.

• Forcible break

A debug interrupt is generated by an external input signal.

• Software break

A debug interrupt is generated when the

brk

instruction is executed.

When a debug interrupt occurs, the processor performs the following processing:

(1) Suspends the instructions currently being executed.

(2) Saves the contents of the PC and PSR, and R0, in that order, to the addresses specified below.
PC/PSR

→

DBRAM + 0x0

R0

→

DBRAM + 0x4

(DBRAM: Start address of the work area for debugging in the user RAM)

(3) Loads address 0xfffc00 to PC and branches to the debug interrupt handler routine.

In the interrupt handler routine, the

retd

instruction should be executed at the end of processing to return to the

suspended instructions. When returning from the interrupt by the

retd

instruction, the processor restores the saved

data in order of the R0 and the PC and PSR.
Neither hardware interrupts nor NMI interrupts are accepted during a debug interrupt.

6.5.2 Resource Requirements and Debugging Tools

The on-chip debug function requires a 64-byte work area. For the work area for debugging, refer to the Technical
Manual of each model.

Debugging is performed by connecting a serial ICE to the debug pins of the S1C17 Core and entering debug
commands from the debugger being run on a personal computer. The tools listed below are required for debugging.
• S1C17 Family Serial ICE (S5U1C17001H)
• S1C17 Family C Compiler Package

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Summary of Contents for S1C17 Series

Page 1: ...Rev 1 2 CMOS 16 BIT SINGLE CHIP MICROCONTROLLER S1C17 Family S1C17 Core Manual ...

Page 2: ... any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party When exporting the products or technology described in this material you should comply with the applicable export control laws and regulations and follow the pr...

Page 3: ...a Formats Handled in Operations Between Memory and a Register 3 2 3 2 1 Unsigned 8 Bit Transfer Memory Register 3 3 3 2 2 Signed 8 Bit Transfer Memory Register 3 3 3 2 3 8 Bit Transfer Register Memory 3 3 3 2 4 16 Bit Transfer Memory Register 3 3 3 2 5 16 Bit Transfer Register Memory 3 4 3 2 6 32 Bit Transfer Memory Register 3 4 3 2 7 32 Bit Transfer Register Memory 3 4 4 Address Map 4 1 4 1 Addre...

Page 4: ...ns 5 23 5 11 Coprocessor Instructions 5 24 6 Functions 6 1 6 1 Transition of the Processor Status 6 1 6 1 1 Reset State 6 1 6 1 2 Program Execution State 6 1 6 1 3 Interrupt Handling 6 1 6 1 4 Debug Interrupt 6 1 6 1 5 HALT and SLEEP Modes 6 1 6 2 Program Execution 6 2 6 2 1 Instruction Fetch and Execution 6 2 6 2 2 Execution Cycles and Flags 6 3 6 3 Interrupts 6 6 6 3 1 Priority of Interrupts 6 6...

Page 5: ...rd rs 7 18 cmc rd sign7 7 20 cmp rd rs 7 21 cmp c rd rs 7 21 cmp nc rd rs 7 21 cmp rd sign7 7 23 cmp a rd rs 7 24 cmp a c rd rs 7 24 cmp a nc rd rs 7 24 cmp a rd imm7 7 26 cv ab rd rs 7 27 cv al rd rs 7 28 cv as rd rs 7 29 cv la rd rs 7 30 cv ls rd rs 7 31 di 7 32 ei 7 33 ext imm13 7 34 halt 7 35 int imm5 7 36 intl imm5 imm3 7 37 jpa rb 7 38 jpa d rb 7 38 jpa imm7 7 39 jpa d imm7 7 39 jpr rb 7 40 ...

Page 6: ...60 ld rb rs 7 60 ld sp imm7 rs 7 62 ld imm7 rs 7 63 ld a rd pc 7 64 ld a rd rs 7 65 ld a rd sp 7 66 ld a rd rb 7 67 ld a rd rb 7 68 ld a rd rb 7 68 ld a rd rb 7 68 ld a rd sp 7 70 ld a rd sp 7 71 ld a rd sp 7 71 ld a rd sp 7 71 ld a rd sp imm7 7 73 ld a rd imm7 7 74 ld a rd imm7 7 75 ld a sp rs 7 76 ld a sp imm7 7 77 ld a rb rs 7 78 ld a rb rs 7 79 ld a rb rs 7 79 ld a rb rs 7 79 ld a sp rs 7 81 l...

Page 7: ...d rs 7 110 not nc rd rs 7 110 not rd sign7 7 111 or rd rs 7 112 or c rd rs 7 112 or nc rd rs 7 112 or rd sign7 7 113 ret 7 114 ret d 7 114 retd 7 115 reti 7 116 reti d 7 116 sa rd rs 7 117 sa rd imm7 7 118 sbc rd rs 7 119 sbc c rd rs 7 119 sbc nc rd rs 7 119 sbc rd imm7 7 120 sl rd rs 7 121 sl rd imm7 7 122 slp 7 123 sr rd rs 7 124 sr rd imm7 7 125 sub rd rs 7 126 sub c rd rs 7 126 sub nc rd rs 7 ...

Page 8: ...CONTENTS vi Seiko Epson Corporation S1C17 CORE MANUAL REV 1 2 Appendix List of S1C17 Core Instructions Ap 1 Revision History ...

Page 9: ...sor type Seiko Epson original 16 bit RISC processor 0 35 0 15 µm low power CMOS process technology Operating clock frequency 90 MHz maximum depending on the processor model and process technology Instruction set Code length 16 bit fixed length Number of instructions 111 basic instructions 184 including variations Execution cycle Main instructions executed in one cycle Extended immediate instructio...

Page 10: ...ess refer ences 24 bit memory space can be accessed directly At initial reset the contents of the general purpose registers are set to 0 2 2 Program Counter PC Symbol PC Size 24 bits Initial value Reset vector Register name Program Counter R W R The Program Counter hereinafter referred to as the PC is a 24 bit counter for holding the address of an instruc tion to be executed More specifically the ...

Page 11: ... When IE bit 0 the processor disables maskable external interrupts When an interrupt is accepted the PSR is saved to the stack and this bit is cleared to 0 However the PSR is not saved to the stack for debug interrupts nor is this bit cleared to 0 C bit 3 Carry This bit indicates a carry or borrow More specifically this bit is set to 1 when in an add or subtract instruction in which the result of ...

Page 12: ... are added together the operation resulted in a 1 negative in the sign bit most sig nificant bit of the result 3 When a negative integer is subtracted from a positive integer the operation resulted in producing a 1 nega tive in the sign bit most significant bit of the result 4 When a positive integer is subtracted from a negative integer the operation resulted in producing a 0 positive in the sign...

Page 13: ...rmore as the SP becomes 0x000000 when it is initialized upon reset last stack address 4 with 2 low order bits 0 must be written to the SP in the beginning part of the initialization routine A load instruction may be used to write this address If an interrupt occurs before the stack is set up it is possible that the PC or PSR will be saved to an indeterminate location and normal operation of a prog...

Page 14: ...the contents of the two registers before they are altered by interrupt handling The PC and PSR data is saved into the stack as shown in the diagram below For returning from the handler routine the reti instruction is used to restore the contents of the PC and PSR from the stack In the reti instruction the PC and PSR are read out of the stack and the SP address is altered as shown in the diagram be...

Page 15: ... 7 0 0xffffff 0x000000 SP SP 4 7 0 0xffffff 0x00 R0 23 16 R0 15 8 R0 7 0 0x000000 Figure 2 4 4 1 SP and Stack 5 Restoring register data from the stack Example ld a r0 sp 1 SP R0 2 SP SP 4 SP 7 0 0xffffff 0x000000 SP SP 4 7 0 0xffffff 0x00 R0 23 16 0x00 R0 23 16 R0 15 8 R0 7 0 R0 15 8 R0 7 0 0x000000 Figure 2 4 4 2 SP and Stack 6 In addition to the instructions shown above some other load instructi...

Page 16: ...ory addresses can be used Post increment function Example ld rd rb 1 ld rd rb 2 rb rb 2 The base address is incremented by an amount equal to the accessed size after the memory has been ac cessed Post decrement function Example ld a rd rb 1 ld a rd rb 2 rb rb 4 The base address is decremented by an amount equal to the accessed size after the memory has been ac cessed Pre decrement function Example...

Page 17: ...tended is determined by the load instruction used In a 16 bit or 8 bit data transfer using a general purpose register as the source the data to be transferred is stored in the low order 16 bits or the low order 8 bits of the source register The data transfer sizes and types are described below 3 1 1 Unsigned 8 Bit Transfer Register Register Example ld ub rd rs rs X 23 16 X 15 8 Byte 7 0 23 16 15 8...

Page 18: ...ister Whether the data will be sign or zero extended is determined by the load instruction used In a 16 bit or 8 bit data transfer using a general purpose register as the source the data to be transferred is stored in the low order 16 bits or the low order 8 bits of the source register Memory is accessed in little endian format one byte 16 bits or 32 bits at a time If memory is to be accessed in 1...

Page 19: ... 15 8 Byte 7 0 rd S S S S S S S S S S Byte 23 16 0 0 0 0 0 0 0 0 0 Figure 3 2 2 1 Signed 8 Bit Transfer Memory Register Bits 15 8 in the destination register are sign extended and bits 23 16 are set to 0x00 3 2 3 8 Bit Transfer Register Memory Example ld b rb rs rs X 23 16 X 15 8 Byte 7 0 Byte 7 0 rb Figure 3 2 3 1 8 Bit Transfer Register Memory 3 2 4 16 Bit Transfer Memory Register Example ld rd ...

Page 20: ... Memory 3 2 6 32 Bit Transfer Memory Register Example ld a rd rb rb 0b 00 Byte 0 7 8 16 15 Byte 0 Byte 1 23 Byte 2 0 0b 01 Byte 1 0b 10 Byte 2 rd 7 0 0b 11 Byte 3 Ignored after read Figure 3 2 6 1 32 Bit Transfer Memory Register 3 2 7 32 Bit Transfer Register Memory Example ld a rb rs rb 0b 00 Byte 0 7 7 8 0 0 16 15 Byte 0 Byte 1 23 Byte 2 0 0b 01 Byte 1 0b 10 Byte 2 0b 11 0x00 rs Figure 3 2 7 1 3...

Page 21: ...eserved as an I O area for the core In addition to this area a 64 byte area located in the user RAM is required for debugging Figure 4 1 1 shows the address space of the S1C17 Core 0xff ffff 0xff fc00 0xff fbff 0x00 0000 Reserved core I O area Figure 4 1 1 Address Space of the S1C17 Core The boot address and debug RAM address depend on the specifications of each the S1C17 Series models Refer to th...

Page 22: ... the vector table Refer to the Technical Manual of each model for the address stored in this register 4 2 2 Processor ID Register IDIR 0xffff84 Name Address Register name Bit Function Setting Init R W Remarks 0x10 IDIR7 IDIR0 D7 D0 Processor ID 0x10 S1C17 Core 0x10 R FFFF84 B Processor ID register This is a read only register that contains the ID code to represent a processor model The S1C17 Core ...

Page 23: ...gn extended Memory 16 bits general purpose register Memory address post increment post decrement and pre decrement functions can be used Stack 16 bits general purpose register Memory 16 bits general purpose register General purpose register 16 bits memory Memory address post increment post decrement and pre decrement functions can be used General purpose register 16 bits stack General purpose regi...

Page 24: ...ry 16 bit comparison between general purpose registers Supports conditional execution c executed if C 1 nc executed if C 0 16 bit comparison of general purpose register and immediate 24 bit comparison between general purpose registers Supports conditional execution c executed if C 1 nc executed if C 0 24 bit comparison of general purpose register and immediate 16 bit comparison with carry between ...

Page 25: ...ible PC relative conditional jump Branch condition C Delayed branching possible PC relative conditional jump Branch condition Z C Delayed branching possible PC relative conditional jump Branch condition Z Delayed branching possible PC relative conditional jump Branch condition Z Delayed branching possible PC relative subroutine call Delayed call possible Absolute subroutine call Delayed call possi...

Page 26: ...register destination Memory addressed by general purpose register Memory addressed by general purpose register with address post incremented Memory addressed by general purpose register with address post decremented Memory addressed by general purpose register with address pre decremented Stack pointer Stack Stack with address post incremented Stack with address post decremented Stack with address...

Page 27: ...immediate sign7 can represent values in the range of 63 to 64 0b0111111 to 0b1000000 Except in the case of shift related instructions immediate data can be extended to a maximum of 24 bits by a com bined use of the operand value and the ext instruction Example ext imm13 1 ext imm13 2 ld a r0 imm7 Load 24 bit data r0 after execution imm13 3 0 1 r0 23 20 19 imm13 2 7 imm7 6 0 5 2 2 Register Direct A...

Page 28: ...ecrement or Pre decrement As in register indirect addressing the memory location to be accessed is specified indirectly by a general purpose register or the stack pointer In this addressing mode the base address held in a specified register is incremented decremented by an amount equal to the transferred data size before or after a data transfer In this way data can be read from or written to cont...

Page 29: ... accessed is rb imm13 5 2 6 Signed PC Relative Addressing This addressing mode is used for the jpr jr and call instructions that have a signed 7 or 10 bit immediate sign7 sign10 or rb in their operand When these instructions are executed the program branches to the address derived by twice adding the sign7 sign10 value 16 bit boundary or the rb register value to the current PC Example PC 0 jrne 0x...

Page 30: ...tructions have been de scribed sequentially the last two are effective and others are ignored When an instruction which does not support the extension in the ext instruction follows an ext the ext instruc tion will be executed as a nop instruction 5 3 1 Extension of Immediate Addressing Extension of imm7 The imm7 immediate is extended to a 16 20 or 24 bit immediate Extending to a 16 bit immediate ...

Page 31: ...nt of the rs register and the immediate specified by an ext instruction according to the arithmetic operation to be performed They then store the result in the rd reg ister The content of the rd register does not affect the arithmetic operation performed An example of how to extend for an add operation is shown below Extending to rs imm13 for 16 bit and 24 bit operation instructions To extend to r...

Page 32: ...diate specified by an ext instruction to the ad dress that is indirectly referenced by rb Adding a 13 bit immediate Memory is accessed at the address derived by adding the 13 bit immediate specified by imm13 to the address specified by the rb register During address calculation imm13 is zero extended to 24 bit quantity Example ext imm13 ld b rd rb ld b rd rb imm13 0 0 0 0 0 0 0 0 0 0 0 23 13 12 im...

Page 33: ...ate 23 Stack pointer 0 SP 5 3 5 Extension of Signed PC Relative Addressing Extending the displacement of PC relative branch instructions The sign7 immediate in PC relative branch instructions is extended to a signed 21 bit or a signed 24 bit im mediate The sign7 immediate in PC relative branch instructions is multiplied by 2 for conversion to a relative value for the jump address and the derived v...

Page 34: ...t quantity using one ext instruction Example ext imm13 call sign10 call sign24 0 0 0 23 11 10 imm13 S sign10 0 Immediate 23 Current address 0 PC 23 New address 0 1 PC 5 3 6 Extension of PC Absolute Addressing Extending the branch destination address The imm7 immediate is extended to a 20 or 24 bit immediate Extending to a 20 bit immediate To extend the immediate to 20 bit quantity enter one ext in...

Page 35: ...ata is sign extended to 16 bits In unsigned byte transfers the source data is zero extended to 16 bits In transfers in which data is transferred from registers data of a specified size on the lower side of the register is the data to be transferred If the destination of transfer is a general purpose register the register content after a transfer is as follows Signed byte data transfer Extended wit...

Page 36: ...ditional execution The logical operation instructions for between registers op rd rs allow use of the switches to specify whether the instruction will be executed or not depending on the C flag status Unconditional execution instructions op rd rs op and or xor not The instruction without a switch will be always executed regardless how the C flag is set Example and rd rs Instructions executable und...

Page 37: ... compares two operands and may alter a flag depending on the comparison result Basically it is used to set conditions for conditional jump instructions If an immediate smaller than operation unit in size is specified as the source it is sign extended when comparison is performed Conditional execution The arithmetic operation instructions for between registers op rd rs allow use of the switches to ...

Page 38: ...5 or the rs reg ister rs imm7 0 3 Shift 0 to 3 bits rs imm7 4 7 Shift 4 bits fixed rs imm7 8 or more Shift 8 bits fixed Example sr rd 1 Bits 15 0 in rd logically shifted one bit to the right sl rd 7 Bits 15 0 in rd logically shifted four bits to the left sa rd 0xf Bits 15 0 in rd arithmetically shifted eight bits to the right 15 0 C rd sr Logical shift right 0 0 15 C rd 15 0 C rd sa Arithmetic shi...

Page 39: ... PC is a signed 8 bit 11 bit quantity derived by doubling sign7 10 least significant bit always 0 When the rb register is used to specify the displacement the register contents are added to the PC without doubling The specifiable displacement can be extended by the ext instruction as shown below For branch instructions used singly jr sign7 Functions as jr sign8 sign8 sign7 0 For the jr instruction...

Page 40: ...er bits of sign24 S 0 11 10 imm13 sign10 0 sign24 23 1 2 0 0 Current address PC Branch destination address PC The range of addresses to which jumped is PC 8 388 606 to PC 8 388 608 When extended by two ext instructions ext imm13 ext imm13 jr sign7 Functions as jr sign24 The imm13 specified by the first ext instruction is effective for only 3 bits from bit 2 to bit 0 with the 10 high order bits ign...

Page 41: ...arison of two values by the cmp instruc tion to determine whether to branch For this reason the name of each instruction includes a character that rep resents relative magnitude The types of conditional jump instructions and branch conditions are listed in Table 5 8 1 1 Table 5 8 1 1 Conditional Jump Instructions and Branch Conditions jrgt jrge jrlt jrle jrugt jruge jrult jrule jreq jrne Greater T...

Page 42: ...is loaded into the PC its least significant bit is always made 0 Refer to the 2 Absolute jump instructions 5 Software interrupts The software interrupts int and intl are the instructions that cause the software to generate an interrupt with the vector numbers specified by the operand imm5 by which a specified interrupt handler routine can be ex ecuted When a software interrupt occurs the processor...

Page 43: ...ss of whether the delayed branch instruction used is con ditional or unconditional and whether it branches In non delayed branch instructions those not followed by the extension d the instruction at the address next to the branch instruction is not executed if the program branches however if it is a conditional jump and the program does not branch the instruction at the next address is executed as...

Page 44: ...op Only increments the PC with no other operations performed halt Places the processor in HALT mode slp Places the processor in SLEEP mode ei Enables interrupts di Disables interrupts For details on HALT and SLEEP modes refer to Section 6 4 Power Down Mode and the Technical Manual for each S1C17 model For details on the interrupt control refer to Section 6 3 Interrupts ...

Page 45: ... bit data into 24 bit data with sign extended rs rd 23 16 15 0 S S S S S S S S S S X 23 16 15 Word 0 15 16 bits 0 cv al rd rs Extracts the high order 8 bits to convert 32 bit data into 24 bit data rs rd 23 16 15 0 23 8 7 0 15 Unchanged 0 X 8 bits 8 bits cv la rd rs Extracts the high order 8 bits to convert 24 bit data into 32 bit data rs rd 23 8 0 23 16 15 0 7 0 X 8 bits 8 bits 0 0 0 0 0 0 0 0 0 0...

Page 46: ...d ld ca instructions send two 24 bit data set in the rd data 0 and rs data 1 registers to the copro cessor Data 1 can also be specified in an immediate imm7 In this case the 7 bit immediate can be extended into imm20 or imm24 using the ext instruction The ld ca instruction inputs the results from the coprocessor to the rd register The ld ca and ld cf instructions input the flag status from the cop...

Page 47: ...ly The processor state transits to another when an interrupt occurs or the slp or halt instruction is executed 6 1 3 Interrupt Handling When a software or other interrupt occurs the processor enters an interrupt handling state The following are the possible causes of the need for interrupt handling 1 External interrupt 2 Software interrupt 3 Address misaligned interrupt 4 NMI 6 1 4 Debug Interrupt...

Page 48: ...6 2 1 Instruction Fetch and Execution Internally in the S1C17 Core instructions are processed in three pipelined stages so that the basic instructions except for the branch instructions and data transfer instructions with the memory address increment decrement function can be executed in one clock cycle Pipelining speeds up instruction processing by executing one instruction while fetching another...

Page 49: ...us Classification Data transfer ld b ld ub ld ld a rd rs rd rb rd rb rd rb rd rb rd sp imm7 rd imm7 rb rs rb rs rb rs rb rs sp imm7 rs imm7 rs rd rs rd rb rd rb rd rb rd rb rd sp imm7 rd imm7 rd rs rd sign7 rd rb rd rb rd rb rd rb rd sp imm7 rd imm7 rb rs rb rs rb rs rb rs sp imm7 rs imm7 rs rd rs rd imm7 rd rb rd rb rd rb rd rb rd sp imm7 rd imm7 rb rs rb rs rb rs rb rs sp imm7 rs imm7 rs rd sp r...

Page 50: ...p rs sp rs sp rs sp imm7 rd rs rd rs rd rs rd imm7 rd rs rd rs rd rs sp rs rd imm7 sp imm7 rd rs rd rs rd rs rd imm7 rd rs rd rs rd rs rd imm7 rd rs rd rs rd rs sp rs rd imm7 sp imm7 rd rs rd rs rd rs rd imm7 rd rs rd rs rd rs rd sign7 rd rs rd rs rd rs rd imm7 rd rs rd rs rd rs rd sign7 rd rs rd rs rd rs rd sign7 rd rs rd rs rd rs rd sign7 rd rs rd rs rd rs rd sign7 rd rs rd rs rd rs rd sign7 Mne...

Page 51: ... rd imm7 rd rs rd imm7 rd rs rd imm7 rd rs imm13 rd rs rd rs rd rs rd rs rd rs sign10 rb imm7 rb sign7 sign7 sign7 sign7 sign7 sign7 sign7 sign7 sign7 sign7 sign10 rb imm7 rb imm5 imm5 imm3 rd rs rd imm7 rd rs rd imm7 rd rs rd imm7 Mnemonic Remark 2 2 cycles when not jumped 3 cycles when jumped 3 When a 1 cycle delayed slot instruction follows Same values as one without d when a 2 cycle delayed sl...

Page 52: ... of priority beginning with the one that has the highest priority When an interrupt occurs the processor disables interrupts that would occur thereafter and performs interrupt handling To support multiple interrupts or another interrupt from within an interrupt set the IE flag in the PSR to 1 in the interrupt handler routine to enable interrupts during interrupt handling Basically even when multip...

Page 53: ...errupt handling performed by the processor is outlined below 1 Suspends the instructions currently being executed An interrupt is generated synchronously with the rising edge of the system clock at the end of the cycle of the currently executed instruction 2 Saves the contents of the PC and PSR to the stack SP in that order 3 Clears the IE interrupt enable bit in the PSR to disable maskable interr...

Page 54: ...interrupt level field in the PSR The interrupt levels 0 7 in the IL field dictate the interrupt levels that can be accepted by the processor and only interrupts with priority levels higher than that are accepted Interrupts with the same interrupt level as IL cannot be accepted The IE flag can be set in the software When an interrupt occurs the IE flag is cleared to 0 interrupts disabled after the ...

Page 55: ...en the ext instruction and the next instruction 2 Between a delayed branch d instruction and the delayed slot instruction that follows 3 Between the retd instruction and the next instruction located at the return address 4 Between the reti or reti d 1 instruction and the next instruction located at the return address 2 5 Between the int ei di slp or halt instruction and the next instruction 2 6 Be...

Page 56: ...ual of each model for details Canceling HALT or SLEEP mode Initial reset is one cause that can bring the processor out of HALT or SLEEP mode Other causes depend on the implementation of the clock control circuit outside the S1C17 Core Initial reset maskable external interrupts NMI and debug interrupts are commonly used for canceling HALT and SLEEP modes The interrupt enable disable status set in t...

Page 57: ...sses specified below PC PSR DBRAM 0x0 R0 DBRAM 0x4 DBRAM Start address of the work area for debugging in the user RAM 3 Loads address 0xfffc00 to PC and branches to the debug interrupt handler routine In the interrupt handler routine the retd instruction should be executed at the end of processing to return to the suspended instructions When returning from the interrupt by the retd instruction the...

Page 58: ...r mode D 7 5 Reserved D4 DR Debug Request Flag Indicates whether an external debug request has occurred or not 1 R Occurred 0 R Not occurred default 1 W Flag is reset 0 W Has no effect This flag is cleared reset to 0 by writing 1 The flag must be cleared before the debug handler routine has been terminated by executing the retd instruction D3 IBE1 Instruction Break 1 Enable Bit Enables disables in...

Page 59: ... Remarks RXDEN TDBE RDBF D7 3 D2 D1 D0 Reserved Receive disable Transmit data buffer empty flag Receive data buffer full flag 1 1 0 R W R R 0 when being read FFFFC0 B Serial status register for debugging 1 Disable 0 Enable 1 Empty 0 Not empty 1 Full 0 Not full D 7 3 Reserved D2 RXDEN Receive Disable Bit Enables disables receive operation in the serial interface for the on chip debug monitor 1 R W ...

Page 60: ... Specification for register indirect addressing with post increment rb sp Specification for register indirect addressing with post decrement rb sp Specification for register indirect addressing with pre decrement sp immX Specification for register indirect addressing with a displacement imm7 Specification for a memory address with an immediate data B XXX An address specified with XXX or the byte d...

Page 61: ...TRUCTIONS 7 2 Seiko Epson Corporation S1C17 CORE MANUAL REV 1 2 Flags IL Interrupt level IE Interrupt enable flag C Carry flag V Overflow flag Z Zero flag N Negative flag Not changed Set 1 or reset 0 1 Set 1 0 Reset 0 ...

Page 62: ...formed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 3 Extension 2 ext imm3 imm3 2 0 imm16 15 13 ext imm13 imm16 12 0 adc rd rs rd rs imm16 C The 16 bit immediate imm16 and C carry flag are added to the content of the rs register and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of th...

Page 63: ...ag are added to the rd register after being zero extended The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext imm9 imm9 8 0 imm16 15 7 adc rd imm7 rd rd imm16 C imm7 imm16 6 0 The 16 bit immediate imm16 and C carry flag are added to the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 3 Delay...

Page 64: ...e rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 3 Extension 2 ext imm3 imm3 2 0 imm16 15 13 ext imm13 imm16 12 0 add rd rs rd rs imm16 The 16 bit immediate imm16 is added to the content of the rs register and the result is loaded into the rd register The operation is performed in 16 bit size and bi...

Page 65: ... added to the rd register after being zero extended The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext imm9 imm9 8 0 imm16 15 7 add rd imm7 rd rd imm16 imm7 imm16 6 0 The 16 bit immediate imm16 is added to the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 3 Delayed slot instruction This i...

Page 66: ...is loaded into the rd register The content of the rs register is not altered 3 Extension 2 ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 add a rd rs rd rs imm24 The 24 bit immediate imm24 is added to the content of the rs register and the result is loaded into the rd register The content of the rs register is not altered 4 Conditional execution The c or nc suffix on the opcode specifies co...

Page 67: ...ed to the rd register after being zero extended 2 Extension 1 ext imm13 imm20 19 7 add a rd imm7 rd rd imm20 imm7 imm20 6 0 The 20 bit immediate imm20 is added to the rd register after being zero extended 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 add a rd imm7 rd rd imm24 imm7 imm24 6 0 The 24 bit immediate imm24 is added to the rd register 4 Delayed slot instruction This in...

Page 68: ...nt of the rs register after being zero extended and the result is loaded into the stack pointer SP The content of the rs register is not altered 3 Extension 2 ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 add a sp rs sp rs imm24 The 24 bit immediate imm24 is added to the content of the rs register and the result is loaded into the stack pointer SP The content of the rs register is not alte...

Page 69: ...ded 2 Extension 1 ext imm13 imm20 19 7 add a sp imm7 sp sp imm20 imm7 imm20 6 0 The 20 bit immediate imm20 is added to the stack pointer SP after being zero extended 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 add a sp imm7 sp sp imm24 imm7 imm24 6 0 The 24 bit immediate imm24 is added to the stack pointer SP 4 Delayed slot instruction This instruction may be executed as a del...

Page 70: ...sult is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 3 Extension 2 ext imm3 imm3 2 0 imm16 15 13 ext imm13 imm16 12 0 and rd rs rd rs imm16 The content of the rs register and the 16 bit immediate imm16 are logically AND ed and the result is loaded into the rd register The operation...

Page 71: ...d and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext imm9 imm9 8 0 sign16 15 7 and rd sign7 rd rd sign16 sign7 sign16 6 0 The content of the rd register and the 16 bit immediate sign16 are logically AND ed and the result is loaded into the rd register The operation is performed in 16 bit size and ...

Page 72: ... handler routine The brk instruction stores the address PC 2 that follows this instruction the contents of the PSR and the contents of the R0 register into the work area for debugging DBRAM then sets the mini monitor start address 0xfffc00 to the PC Thus the program branches to the debug handler routine Furthermore the processor enters the debug mode The retd instruction must be used for return fr...

Page 73: ... instruction is executed in the subroutine the program flow returns to the instruction following the call instruction 2 Delayed branch d bit bit 7 1 call d rb When call d rb is specified the d bit bit 7 in the instruction code is set and the following instruction becomes a delayed slot instruction The delayed slot instruction is executed before branching to the subroutine Therefore the address PC ...

Page 74: ... of PC 1 022 to PC 1 024 2 Extension 1 ext imm13 sign24 23 11 call sign10 call sign24 sign10 sign24 10 1 sign24 0 0 The ext instruction extends the displacement into 24 bits using its 13 bit immediate imm13 The 24 bit displacement is added to the PC The sign24 allows branches within the range of PC 8 388 606 to PC 8 388 608 3 Delayed branch d bit bit 10 1 call d sign10 When call d sign10 is specif...

Page 75: ...the subroutine the program flow returns to the instruction following the calla instruction 2 Delayed branch d bit bit 7 1 calla d rb When calla d is specified the d bit bit 7 in the instruction code is set and the following instruction becomes a delayed slot instruction The delayed slot instruction is executed before branching to the subroutine Therefore the address PC 4 of the instruction that fo...

Page 76: ...l imm7 call imm20 imm7 imm20 6 0 The ext instruction extends the destination address into 20 bits using its 13 bit immediate imm13 The 20 bit destination address is set to the PC 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 call imm7 call imm24 imm7 imm24 6 0 The 24 bit destination address is set to the PC 4 Delayed branch d bit bit 7 1 calla d imm7 When calla d is specified th...

Page 77: ... and sets or resets the flags C V Z and N according to the results The imm13 is zero extended into 16 bits prior to the operation The operation is performed in 16 bit size It does not change the contents of the rd and rs registers This combination does not use the rd register value for comparison 3 Extension 2 ext imm3 imm3 2 0 imm16 15 13 ext imm13 imm16 12 0 cmc rd rs rs imm16 C Subtracts the co...

Page 78: ...uted as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed Example 1 cmc r0 r1 Changes the flags according to the results of r0 r1 C 2 ext 0x1fff cmc r1 r2 Changes the flags according to the results of r2 0x1fff C ...

Page 79: ... operation The operation is performed in 16 bit size It does not change the contents of the rd register 2 Extension 1 ext imm9 imm9 8 0 sign16 15 7 cmc rd sign7 rd sign16 C sign7 sign16 6 0 Subtracts the contents of the signed 16 bit immediate sign16 and C carry flag from the contents of the rd register and sets or resets the flags C V Z and N according to the results The operation is performed in...

Page 80: ...s the flags C V Z and N according to the results The imm13 is zero extended into 16 bits prior to the operation The operation is performed in 16 bit size It does not change the contents of the rd and rs registers This combination does not use the rd register value for comparison 3 Extension 2 ext imm3 imm3 2 0 imm16 15 13 ext imm13 imm16 12 0 cmp rd rs rs imm16 Subtracts the 16 bit immediate imm16...

Page 81: ...ed as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed Example 1 cmp r0 r1 Changes the flags according to the results of r0 r1 2 ext 0x1 ext 0x1fff Changes the flags according to the results of cmp r1 r2 r2 0x3fff ...

Page 82: ...ation The operation is performed in 16 bit size It does not change the contents of the rd register 2 Extension 1 ext imm9 imm9 8 0 sign16 15 7 cmp rd sign7 rd sign16 sign7 sign16 6 0 Subtracts the signed 16 bit immediate sign16 from the contents of the rd register and sets or resets the flags C V Z and N according to the results The operation is performed in 16 bit size It does not change the cont...

Page 83: ...rs register and sets or resets the flags C and Z according to the results The imm13 is zero extended into 24 bits prior to the operation It does not change the contents of the rd and rs registers This combination does not use the rd register value for comparison 3 Extension 2 ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 cmp a rd rs rs imm24 Subtracts the 24 bit immediate imm24 from the co...

Page 84: ... as a delayed slot instruction by writing it directly after a branch instruction with the d bit In this case extension of the immediate by the ext instruction cannot be performed Example 1 cmp a r0 r1 Changes the flags according to the results of r0 r1 2 ext 0x1 ext 0x1fff cmp a r1 r2 Changes the flags according to the results of r2 0x3fff ...

Page 85: ...0 Subtracts the 20 bit immediate imm20 from the contents of the rd register and sets or resets the flags C and Z according to the results The imm20 is zero extended into 24 bits prior to the operation It does not change the contents of the rd register 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 cmp a rd imm7 rd imm24 imm7 imm24 6 0 Subtracts the 24 bit immediate imm24 from the...

Page 86: ... Src Register direct rs r0 to r7 Dst Register direct rd r0 to r7 CLK One cycle Description 1 Standard The eight low order bits of the rs register are transferred to the rd register after being sign extended to 24 bits rs rd X 23 8 7 0 23 8 8 bits 7 0 S S S S S S S S S S S S S S S S S S Byte 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it dire...

Page 87: ... Src Register direct rs r0 to r7 Dst Register direct rd r0 to r7 CLK One cycle Description 1 Standard The eight low order bits of the rs register are transferred to the eight high order bits of the rd register rs rd 23 16 15 0 23 8 7 0 15 Unchanged 0 X 8 bits 8 bits 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instr...

Page 88: ... N Mode Src Register direct rs r0 to r7 Dst Register direct rd r0 to r7 CLK One cycle Description 1 Standard The 16 low order bits of the rs register are transferred to the rd register after being sign extended to 24 bits rs rd 23 16 15 0 S S S S S S S S S S X 23 16 15 Word 0 15 16 bits 0 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it direct...

Page 89: ... to r7 Dst Register direct rd r0 to r7 CLK One cycle Description 1 Standard The eight high order bits of the rs register are transferred to the eight low order bits of the rd register The 16 high order bits of the rd register are set to 0 rs rd 23 8 0 23 16 15 0 7 0 X 8 bits 8 bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 Delayed slot instruction This instruction may be executed as a delayed slot instruc...

Page 90: ...t Register direct rd r0 to r7 CLK One cycle Description 1 Standard Bit 15 sign bit of 16 bit data of the rs register is transferred to the 16 low order bits of the rd register The eight high order bits of the rd register are set to 0 rs rd 23 16 15 0 S 0 0 0 0 0 0 0 0 S S S S S S S S S S S S S S S S X 23 16 15 Word 0 15 0 2 Delayed slot instruction This instruction may be executed as a delayed slo...

Page 91: ...instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit Example di Disables external maskable interrupts Caution Maskable interrupts are disabled from the third cycle after the di instruction has been executed di Instruction 1 1 cycle instruction Instruction 2 1 cycle instruction Instruction 3 Interrupts are disabled from this inst...

Page 92: ...ction by writing it directly after a branch instruction with the d bit Example ei Enables external maskable interrupts Caution Maskable interrupts are enabled from the third cycle after the ei instruction has been executed ei Instruction 1 1 cycle instruction Instruction 2 1 cycle instruction Instruction 3 Interrupts are enabld from this instruction Example Interrupt disabled periods using the di ...

Page 93: ...e descriptions of each instruction for the extension contents and the usage Interrupts for the ext instruction not including reset and debug break are masked in the hardware and interrupt handling is determined when the target instruction to be extended is executed In this case the return address from interrupt handling is the beginning of the ext instruction Example ext 0x7ff ext 0x1fff add a r1 ...

Page 94: ...maskable external interrupts NMI and debug interrupts are commonly used for canceling HALT mode The interrupt enable disable status set in the processor does not affect the cancellation of HALT mode even if an interrupt signal is used as the cancellation In other words interrupt signals are able to cancel HALT mode even if the IE flag in PSR or the interrupt enable bits in the interrupt controller...

Page 95: ... saves the address of the next instruction and the contents of the PSR into the stack then reads the specified interrupt vector from the vector table and sets it to the PC By this processing the program flow branches to the specified interrupt handler routine imm5 Vector No Vector address Cause of interrupt 0x00 0 TTBR 0x00 Reset interrupt 0x01 1 TTBR 0x04 Address misaligned interrupt 0x02 2 TTBR ...

Page 96: ...he address of the next instruction and the contents of the PSR into the stack then reads the specified interrupt vector from the vector table and sets it to the PC By this processing the program flow branches to the specified interrupt handler routine In addition to this the imm3 value is set to the IL bits in the PSR interrupt level to disable interrupts of which the interrupt level is lower than...

Page 97: ...t address The LSB of the rb register is ignored and is always handled as 0 2 Delayed branch d bit bit 7 1 jpa d rb For the jpa d instruction the next instruction becomes a delayed slot instruction A delayed slot instruction is executed before the program branches Interrupts are masked in intervals between the jpa d instruction and the next instruction so no interrupts occur Example jpa r0 Jumps to...

Page 98: ... address into 20 bits using its 13 bit immediate imm13 The 20 bit destination address is set to the PC 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 jpa imm7 jpa imm24 imm7 imm24 6 0 The 24 bit destination address is set to the PC 4 Delayed branch d bit bit 7 1 jpa d imm7 For the jpa d instruction the next instruction becomes a delayed slot instruction A delayed slot instruction...

Page 99: ...the program branches to that address The LSB of the rb register is ignored and is always handled as 0 2 Delayed branch d bit bit 7 1 jpr d rb For the jpr d instruction the next instruction becomes a delayed slot instruction A delayed slot instruction is executed before the program branches Interrupts are masked in intervals between the jpr d instruction and the next instruction so no interrupts oc...

Page 100: ...ion 1 ext imm13 sign24 23 11 jpr sign10 jpr sign24 sign10 sign24 10 1 sign24 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into 24 bits using its 13 bit immediate imm13 The sign24 allows branches within the range of PC 8 388 606 to PC 8 388608 3 Delayed branch d bit bit 10 1 jpr d sign10 For the jpr d instruction the next instruction becomes a delayed slot instruction...

Page 101: ... sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext imm3 imm3 2 0 sign24 23 21 ext imm13 sign24 20 8 jreq sign7 jreq sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions extend the displace...

Page 102: ... sign7 jrge sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext imm3 imm3 2 0 sign24 23 21 ext imm13 sign24 20 8 jrge sign7 jrge sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions extend t...

Page 103: ...20 8 jrgt sign7 jrgt sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext imm3 imm3 2 0 sign24 23 21 ext imm13 sign24 20 8 jrgt sign7 jrgt sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions...

Page 104: ...20 8 jrle sign7 jrle sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext imm3 imm3 2 0 sign24 23 21 ext imm13 sign24 20 8 jrle sign7 jrle sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions...

Page 105: ... sign7 jrlt sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext imm3 imm3 2 0 sign24 23 21 ext imm13 sign24 20 8 jrlt sign7 jrlt sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions extend t...

Page 106: ... sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext imm3 imm3 2 0 sign24 23 21 ext imm13 sign24 20 8 jrne sign7 jrne sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions extend the displace...

Page 107: ...7 jruge sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext imm3 imm3 2 0 sign24 23 21 ext imm13 sign24 20 8 jruge sign7 jruge sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions extend the...

Page 108: ...rugt sign7 jrugt sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext imm3 imm3 2 0 sign24 23 21 ext imm13 sign24 20 8 jrugt sign7 jrugt sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions e...

Page 109: ...rule sign7 jrule sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext imm3 imm3 2 0 sign24 23 21 ext imm13 sign24 20 8 jrule sign7 jrule sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions e...

Page 110: ...rult sign21 sign7 sign21 7 1 sign21 0 0 The ext instruction extends the displacement to be added to the PC PC 2 into signed 21 bits using its 13 bit immediate data imm13 The sign21 allows branches within the range of PC 1 048 574 to PC 1 048 576 3 Extension 2 ext imm3 imm3 2 0 sign24 23 21 ext imm13 sign24 20 8 jrult sign7 jrult sign24 sign7 sign24 7 1 sign24 0 0 The ext instructions extend the di...

Page 111: ... d 0 0 1 0 r s Flag IL IE C V Z N Mode Src Register direct rs r0 to r7 Dst Register direct rd r0 to r7 CLK One cycle Description 1 Standard The 16 low order bits of the rs register are transferred to the rd register The eight high order bits of the rd register are set to 0 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branc...

Page 112: ...rises the memory address the 16 bit data in which is transferred to the rd register The content of the rb register is not altered The eight high order bits of the rd register are set to 0 3 Extension 2 ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 ld rd rb memory address rb imm24 The addressing mode changes to register indirect addressing with displacement so the content of the rb register...

Page 113: ...2 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 0 r d 0 1 1 0 r b ld rd rb 0 0 1 0 0 0 r d 1 1 1 0 r b ld rd rb 0 0 1 0 0 0 r d 1 0 1 0 r b ld rd rb Flag IL IE C V Z N Mode Src Register indirect rb r0 to r7 Dst Register direct rd r0 to r7 CLK Two cycles Description 1 Address increment decrement option Specifying the or option will automatically increment decrement the memory address This allows the program ...

Page 114: ... set to 0 The memory address will be decremented by imm13 bytes after the data transfer has finished 4 Extension 2 example of pre decrement option ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 ld rd rb source memory address rb imm24 After the memory address specified by the rb register is decremented by imm24 bytes the 16 bit data in the decremented address is transferred to the rd registe...

Page 115: ... with the 20 bit immediate imm20 added comprises the memory address the 16 bit data in which is transferred to the rd register The eight high order bits of the rd register are set to 0 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 ld rd sp imm7 memory address sp imm24 imm7 imm24 6 0 The two ext instructions extend the displacement to a 24 bit quantity As a result the content of ...

Page 116: ...ecified with the 20 bit immediate imm20 is transferred to the rd register The eight high order bits of the rd register are set to 0 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 ld rd imm7 memory address sp imm24 imm7 imm24 6 0 The two ext instructions extend the memory address to a 24 bit quantity As a result the 16 bit data in the memory address specified with the 24 bit immed...

Page 117: ...1 Standard ld rd sign7 rd sign7 sign extended The 7 bit immediate sign7 is loaded to the rd register after being sign extended to a 16 bit quantity 2 Extension 1 ext imm13 sign16 15 7 ld rd sign7 rd sign16 sign7 sign16 6 0 The immediate data is extended into a 16 bit quantity by the ext instruction and it is loaded to the rd register 3 Delayed slot instruction This instruction may be executed as a...

Page 118: ...ed to the address indicated by the content of the rb register with the 13 bit immediate imm13 added The content of the rb register is not altered 3 Extension 2 ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 ld rb rs memory address rb imm24 The addressing mode changes to register indirect addressing with displacement so the 16 low order bits of the rs register are transferred to the address ...

Page 119: ... 0 r b ld rb rs 0 0 1 0 0 1 r s 1 1 1 0 r b ld rb rs 0 0 1 0 0 1 r s 1 0 1 0 r b ld rb rs Flag IL IE C V Z N Mode Src Register direct rs r0 to r7 Dst Register indirect rb r0 to r7 CLK Two cycles Description 1 Address increment decrement option Specifying the or option will automatically increment decrement the memory address This allows the program to simply perform continuous data transfer ld rb ...

Page 120: ...ess will be decremented by imm13 bytes after the data transfer has finished 4 Extension 2 example of pre decrement option ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 ld rb rs Destination memory address rb imm24 After the memory address specified by the rb register is decremented by imm24 bytes the 16 low order bits of the rs register are transferred to the decremented address 5 Delayed s...

Page 121: ...er bits of the rs register are transferred to the address indicated by the content of the SP with the 20 bit immediate imm20 added 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 ld sp imm7 rs memory address sp imm24 imm7 imm24 6 0 The two ext instructions extend the displacement to a 24 bit quantity As a result the 16 low order bits of the rs register are transferred to the addre...

Page 122: ...are transferred to the memory address specified with the 20 bit immediate imm20 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 ld imm7 rs memory address imm24 imm7 imm24 6 0 The two ext instructions extend the memory address to a 24 bit quantity As a result the 16 low order bits of the rs register are transferred to the memory address specified with the 24 bit immediate imm24 4 D...

Page 123: ...LK One cycle Description The content of the PC PC 2 is transferred to the rd register Example ld a r0 pc r0 pc 2 Caution When this instruction is executed a value equal to the PC of this instruction plus 2 is loaded into the register This instruction must be executed as a delayed slot instruction If it does not follow a delayed branch instruction the PC value that is loaded into the rd register ma...

Page 124: ...5 4 3 2 1 0 0 0 1 0 1 0 r d 0 0 1 1 r s Flag IL IE C V Z N Mode Src Register direct rs r0 to r7 Dst Register direct rd r0 to r7 CLK One cycle Description 1 Standard The content of the rs register 24 bit data is transferred to the rd register 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit Exa...

Page 125: ... 23 2 sp 23 2 rd 1 0 0 Extension 1 Unusable Extension 2 Unusable Code 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 1 r d 0 0 1 0 0 0 0 Flag IL IE C V Z N Mode Src Register direct sp Dst Register direct rd r0 to r7 CLK One cycle Description The content of the SP 24 bit data is transferred to the rd register Example ld a r0 sp r0 sp ...

Page 126: ...13 bit immediate imm13 added comprises the memory address the 32 bit data the eight high order bits are ignored in which is transferred to the rd register The content of the rb register is not altered 3 Extension 2 ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 ld a rd rb memory address rb imm24 The addressing mode changes to register indirect addressing with displacement so the content of ...

Page 127: ... imm24 rd 23 0 A rb 23 0 ignored A rb 31 24 Code 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 0 r d 0 1 1 1 r b ld a rd rb 0 0 1 0 0 0 r d 1 1 1 1 r b ld a rd rb 0 0 1 0 0 0 r d 1 0 1 1 r b ld a rd rb Flag IL IE C V Z N Mode Src Register indirect rb r0 to r7 Dst Register direct rd r0 to r7 CLK Two cycles Description 1 Address increment decrement option Specifying the or option will automaticall...

Page 128: ...emory address will be decremented by imm13 bytes after the data transfer has finished 4 Extension 2 example of pre decrement option ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 ld a rd rb source memory address rb imm24 After the memory address specified by the rb register is decremented by imm24 bytes the 32 bit data the eight high order bits are ignored in the decremented address is tran...

Page 129: ... content of the SP with the 13 bit immediate imm13 added comprises the memory address the 32 bit data the eight high order bits are ignored in which is transferred to the rd register The content of the SP is not altered 3 Extension 2 ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 ld a rd sp memory address sp imm24 The addressing mode changes to register indirect addressing with displacement...

Page 130: ...0 imm24 rd 23 0 A sp 23 0 ignored A sp 31 24 Code 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 1 r d 0 1 1 1 0 0 0 ld a rd sp 0 0 1 1 1 1 r d 1 1 1 1 0 0 0 ld a rd sp 0 0 1 1 1 1 r d 1 0 1 1 0 0 0 ld a rd sp Flag IL IE C V Z N Mode Src Register indirect sp Dst Register direct rd r0 to r7 CLK Two cycles Description 1 Address increment decrement option Specifying the or option will automatically ...

Page 131: ...sed The memory address will be decremented by imm13 bytes after the data transfer has finished 4 Extension 2 example of pre decrement option ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 ld rd sp source memory address sp imm24 After the memory address specified by the SP is decremented by imm24 bytes the 32 bit data the eight high order bits are ignored in the decremented address is transf...

Page 132: ... As a result the content of the SP with the 20 bit immediate imm20 added comprises the memory address the 32 bit data the eight high order bits are ignored in which is transferred to the rd register 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 ld a rd sp imm7 memory address sp imm24 imm7 imm24 6 0 The two ext instructions extend the displacement to a 24 bit quantity As a result...

Page 133: ...t data the eight high order bits are ignored in the memory address specified with the 20 bit immediate imm20 is transferred to the rd register 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 ld a rd imm7 memory address imm24 imm7 imm24 6 0 The two ext instructions extend the displacement to a 24 bit quantity As a result the 32 bit data the eight high order bits are ignored in the ...

Page 134: ...ded 2 Extension 1 ext imm13 sign20 19 7 ld a rd imm7 rd imm20 zero extended imm7 imm20 6 0 The immediate data is extended into a 20 bit quantity by the ext instruction and it is loaded to the rd register after being zero extended 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 ld a rd imm7 rd imm24 imm7 imm24 6 0 The immediate data is extended into a 24 bit quantity by the ext ins...

Page 135: ...xtension 2 Unusable Code 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 1 r s 1 0 1 0 0 0 0 Flag IL IE C V Z N Mode Src Register direct rs r0 to r7 Dst Register direct sp CLK One cycle Description The content of the rs register is transferred to the SP Example ld a sp r0 sp r0 Caution In data transfer to the SP the low order two bits of the source data are always handled as 0 ...

Page 136: ...n20 19 7 ld a sp imm7 sp imm20 zero extended imm7 imm20 6 0 The immediate data is extended into a 20 bit quantity by the ext instruction and it is loaded to the SP after being zero extended 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 ld a sp imm7 sp imm24 imm7 imm24 6 0 The immediate data is extended into a 24 bit quantity by the ext instruction and it is loaded to the SP 4 De...

Page 137: ...ng with displacement As a result the content of the rs register is transferred to the address indicated by the content of the rb register with the 13 bit immediate imm13 added The content of the rb register is not altered 3 Extension 2 ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 ld a rb rs memory address rb imm24 The addressing mode changes to register indirect addressing with displaceme...

Page 138: ...3 0 A rb 31 24 0 Code 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 1 r s 0 1 1 1 r b ld a rb rs 0 0 1 0 0 1 r s 1 1 1 1 r b ld a rb rs 0 0 1 0 0 1 r s 1 0 1 1 r b ld a rb rs Flag IL IE C V Z N Mode Src Register direct rs r0 to r7 Dst Register indirect rb r0 to r7 CLK Two cycles Description 1 Address increment decrement option Specifying the or option will automatically increment decrement the m...

Page 139: ...its set to 0 in the memory The memory address will be decremented by imm13 bytes after the data transfer has finished 4 Extension 2 example of pre decrement option ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 ld a rb rs Destination memory address rb imm24 After the memory address specified by the rb register is decremented by imm24 bytes the content of the rs register 24 bit data is trans...

Page 140: ...direct addressing with displacement As a result the content of the rs register is transferred to the address indicated by the content of the SP with the 13 bit immediate imm13 added The content of the SP is not altered 3 Extension 2 ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 ld a sp rs memory address sp imm24 The addressing mode changes to register indirect addressing with displacement ...

Page 141: ...23 0 A sp 31 24 0 Code 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 1 1 1 r s 0 1 1 1 1 0 0 ld a sp rs 0 0 1 1 1 1 r s 1 1 1 1 1 0 0 ld a sp rs 0 0 1 1 1 1 r s 1 0 1 1 1 0 0 ld a sp rs Flag IL IE C V Z N Mode Src Register direct rs r0 to r7 Dst Register indirect sp CLK Two cycles Description 1 Address increment decrement option Specifying the or option will automatically increment decrement the mem...

Page 142: ...its set to 0 in the memory The memory address will be decremented by imm13 bytes after the data transfer has finished 4 Extension 2 example of pre decrement option ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 ld a sp rs Destination memory address sp imm24 After the memory address specified by the SP is decremented by imm24 bytes the content of the rs register 24 bit data is transferred to...

Page 143: ...0 The ext instruction extends the displacement to a 20 bit quantity As a result the content of the rs register is transferred to the address indicated by the content of the SP with the 20 bit immediate imm20 added 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 ld a sp imm7 rs memory address sp imm24 imm7 imm24 6 0 The two ext instructions extend the displacement to a 24 bit quant...

Page 144: ...e displacement to a 20 bit quantity As a result the content of the rs register is transferred to the memory address specified with the 20 bit immediate imm20 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 ld a imm7 rs memory address imm24 imm7 imm24 6 0 The two ext instructions extend the displacement to a 24 bit quantity As a result the content of the rs register is transferred ...

Page 145: ... IL IE C V Z N Mode Src Register direct rs r0 to r7 Dst Register direct rd r0 to r7 CLK One cycle Description 1 Standard The eight low order bits of the rs register are transferred to the rd register after being sign extended to 16 bits The eight high order bits of the rd register are set to 0 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it d...

Page 146: ...ges the addressing mode to register indirect addressing with displacement As a result the content of the rb register with the 13 bit immediate imm13 added comprises the memory address the byte data in which is transferred to the rd register after being sign extended to 16 bits The eight high order bits of the rd register are set to 0 The content of the rb register is not altered 3 Extension 2 ext ...

Page 147: ...rb 23 0 imm24 rd 7 0 B rb rd 15 8 B rb 7 rd 24 16 0 Code 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 0 r d 0 1 0 0 r b ld b rd rb 0 0 1 0 0 0 r d 1 1 0 0 r b ld b rd rb 0 0 1 0 0 0 r d 1 0 0 0 r b ld b rd rb Flag IL IE C V Z N Mode Src Register indirect rb r0 to r7 Dst Register direct rd r0 to r7 CLK Two cycles Description 1 Address increment decrement option Specifying the or option will auto...

Page 148: ... rd register after being sign extended to 16 bits The rb register contains the memory address to be accessed The eight high order bits of the rd register are set to 0 The memory address will be decremented by imm13 bytes after the data transfer has finished 4 Extension 2 example of pre decrement option ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 ld b rd rb source memory address rb imm24 ...

Page 149: ...imm7 memory address sp imm20 imm7 imm20 6 0 The ext instruction extends the displacement to a 20 bit quantity As a result the content of the SP with the 20 bit immediate imm20 added comprises the memory address the byte data in which is transferred to the rd register after being sign extended to 16 bits The eight high order bits of the rd register are set to 0 3 Extension 2 ext imm4 imm4 3 0 imm24...

Page 150: ...m7 imm20 6 0 The ext instruction extends the displacement to a 20 bit quantity As a result the byte data in the memory address specified with the 20 bit immediate imm20 is transferred to the rd register after being sign extended to 16 bits The eight high order bits of the rd register are set to 0 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 ld b rd imm7 memory address imm24 imm...

Page 151: ...nges the addressing mode to register indirect addressing with displacement As a result the eight low order bits of the rs register are transferred to the address indicated by the content of the rb register with the 13 bit immediate imm13 added The content of the rb register is not altered 3 Extension 2 ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 ld b rb rs memory address rb imm24 The add...

Page 152: ...0 r b ld b rb rs 0 0 1 0 0 1 r s 1 1 0 0 r b ld b rb rs 0 0 1 0 0 1 r s 1 0 0 0 r b ld b rb rs Flag IL IE C V Z N Mode Src Register direct rs r0 to r7 Dst Register indirect rb r0 to r7 CLK Two cycles Description 1 Address increment decrement option Specifying the or option will automatically increment decrement the memory address This allows the program to simply perform continuous data transfer l...

Page 153: ... of the rs register are transferred to the specified memory location The rb register contains the memory address to be accessed The memory address will be decremented by imm13 bytes after the data transfer has finished 4 Extension 2 example of pre decrement option ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 ld b rb rs Destination memory address rb imm24 After the memory address specified...

Page 154: ...7 rs memory address sp imm20 imm7 imm20 6 0 The ext instruction extends the displacement to a 20 bit quantity As a result the eight low order bits of the rs register are transferred to the address indicated by the content of the SP with the 20 bit immediate imm20 added 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 ld b sp imm7 rs memory address sp imm24 imm7 imm24 6 0 The two ex...

Page 155: ...mm20 6 0 The ext instruction extends the displacement to a 20 bit quantity As a result the eight low order bits of the rs register are transferred to the memory address specified with the 20 bit immediate imm20 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 ld b imm7 rs memory address imm24 imm7 imm24 6 0 The two ext instructions extend the displacement to a 24 bit quantity As a ...

Page 156: ... 1 r s Flag IL IE C V Z N Mode Src Register direct rs r0 to r7 Dst Register direct rd r0 to r7 CLK One cycle Description 1 Standard ld ca rd rs co_dout0 data rd co_dout1 data rs Transfers data set in the rd and rs registers to the coprocessor and gets the operation results by the coprocessor The results are loaded to the rd register and the C V Z and N flags in the PSR 2 Delayed slot instruction T...

Page 157: ... flags in the PSR 2 Extension 1 ext imm13 imm20 19 7 ld ca rd imm7 co_dout0 data rd co_dout1 data imm20 imm7 imm20 6 0 The ext instruction extends the immediate to a 20 bit quantity As a result data set in the rd register and 20 bit immediate imm20 are transferred to the coprocessor and the results are loaded to the rd register and the C V Z and N flags in the PSR 3 Extension 2 ext imm4 imm4 3 0 i...

Page 158: ...0 0 1 1 0 1 r d 0 0 0 1 r s Flag IL IE C V Z N Mode Src Register direct rs r0 to r7 Dst Register direct rd r0 to r7 CLK One cycle Description 1 Standard ld cf rd rs co_dout0 data rd co_dout1 data rs Transfers data set in the rd and rs registers to the coprocessor and gets the flag status of the coprocessor to the C V Z and N flags in the PSR 2 Delayed slot instruction This instruction may be execu...

Page 159: ...Extension 1 ext imm13 imm20 19 7 ld cf rd imm7 co_dout0 data rd co_dout1 data imm20 imm7 imm20 6 0 The ext instruction extends the immediate to a 20 bit quantity As a result data set in the rd register and 20 bit immediate imm20 are transferred to the coprocessor and the flag status is loaded to the C V Z and N flags in the PSR 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 ld cf...

Page 160: ...0 0 1 0 r s Flag IL IE C V Z N Mode Src Register direct rs r0 to r7 Dst Register direct rd r0 to r7 CLK One cycle Description 1 Standard ld cw rd rs co_dout0 data rd co_dout1 data rs Transfers data set in the rd and rs registers to the coprocessor The rd register and the C V Z and N flags in the PSR are not altered 2 Delayed slot instruction This instruction may be executed as a delayed slot instr...

Page 161: ...out0 data rd co_dout1 data imm20 imm7 imm20 6 0 The ext instruction extends the immediate to a 20 bit quantity As a result data set in the rd register and 20 bit immediate imm20 are transferred to the coprocessor The rd register and the C V Z and N flags in the PSR are not altered 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 ld cw rd imm7 co_dout0 data rd co_dout1 data imm24 im...

Page 162: ... IL IE C V Z N Mode Src Register direct rs r0 to r7 Dst Register direct rd r0 to r7 CLK One cycle Description 1 Standard The eight low order bits of the rs register are transferred to the rd register after being zero extended to 16 bits The eight high order bits of the rd register are set to 0 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it d...

Page 163: ...ng mode to register indirect addressing with displacement As a result the content of the rb register with the 13 bit immediate imm13 added comprises the memory address the byte data in which is transferred to the rd register after being zero extended to 16 bits The eight high order bits of the rd register are set to 0 The content of the rb register is not altered 3 Extension 2 ext imm11 imm11 10 0...

Page 164: ... 7 0 B rb rd 15 8 0 rd 24 16 0 Code 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 0 r d 0 1 0 1 r b ld ub rd rb 0 0 1 0 0 0 r d 1 1 0 1 r b ld ub rd rb 0 0 1 0 0 0 r d 1 0 0 1 r b ld ub rd rb Flag IL IE C V Z N Mode Src Register indirect rb r0 to r7 Dst Register direct rd r0 to r7 CLK Two cycles Description 1 Address increment decrement option Specifying the or option will automatically incremen...

Page 165: ...e rd register after being zero extended to 16 bits The rb register contains the memory address to be accessed The eight high order bits of the rd register are set to 0 The memory address will be decremented by imm13 bytes after the data transfer has finished 4 Extension 2 example of pre decrement option ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 ld ub rd rb source memory address rb imm2...

Page 166: ...dress sp imm20 imm7 imm20 6 0 The ext instruction extends the displacement to a 20 bit quantity As a result the content of the SP with the 20 bit immediate imm20 added comprises the memory address the byte data in which is transferred to the rd register after being zero extended to 16 bits The eight high order bits of the rd register are set to 0 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm...

Page 167: ... 0 The ext instruction extends the displacement to a 20 bit quantity As a result the byte data in the memory address specified with the 20 bit immediate imm20 is transferred to the rd register after being zero extended to 16 bits The eight high order bits of the rd register are set to 0 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 ld ub rd imm7 memory address imm24 imm7 imm24 6...

Page 168: ... 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Flag IL IE C V Z N Mode CLK One cycle Description 1 Standard The nop instruction just takes one cycle and no operation results The PC is incremented 2 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by writing it directly after a branch instruction with the d bit Example nop nop Waits 2 cycles ...

Page 169: ...reversed after zero extended into 16 bits and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 3 Extension 2 ext imm3 imm3 2 0 imm16 15 13 ext imm13 imm16 12 0 not rd rs rd imm16 All the bits of the 16 bit immediate imm16 are reversed and the result is loaded into the rd register The operation is performed in 16 bit ...

Page 170: ...6 bits and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext imm9 imm9 8 0 sign16 15 7 not rd sign7 rd sign16 sign7 sign16 6 0 All the bits of the sign extended 16 bit immediate sign16 are reversed and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 ...

Page 171: ...loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 3 Extension 2 ext imm3 imm3 2 0 imm16 15 13 ext imm13 imm16 12 0 or rd rs rd rs imm16 The content of the rs register and the zero extended 16 bit immediate imm16 are logically OR ed and the result is loaded into the rd register The opera...

Page 172: ...ed and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext imm9 imm9 8 0 sign16 15 7 or rd sign7 rd rd sign16 sign7 sign16 6 0 The content of the rd register and the 16 bit immediate sign16 are logically OR ed and the result is loaded into the rd register The operation is performed in 16 bit size and b...

Page 173: ...tine The SP is incremented by four bytes If the SP has been modified in the subroutine it is necessary to return the SP value before executing the ret instruction 2 Delayed branch d bit bit 7 1 ret d For the ret d instruction the next instruction becomes a delayed slot instruction A delayed slot instruction is executed before the program returns from the subroutine Interrupts are masked in interva...

Page 174: ...0 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 0 0 Flag IL IE C V Z N Mode CLK Four cycles Description Restore the contents of the R0 PSR and PC that were saved to the work area for debugging DBRAM when an debug interrupt occurred to the respective registers and return from the debug interrupt handler routine This instruction is provided for debug firmware Do not use it in the user program Exam...

Page 175: ...les other Description 1 Standard reti Restores the contents of the PC and PSR that were saved to the stack when an interrupt occurred to the respective registers and return from the interrupt handler routine The SP is incremented by an amount equivalent to four bytes 2 Delayed branch d bit bit 7 1 reti d For the reti d instruction the next instruction becomes a delayed slot instruction A delayed s...

Page 176: ... r0 to r7 CLK One cycle Description 1 Standard The rd register is shifted as shown in the diagram below The number of bits to be shifted is specified by the rs register value as follows rs 0 3 0 3 bits rs 4 7 4 bits rs 8 or more 8 bits The sign bit is copied to bit 15 of the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 15 rd register after ex...

Page 177: ... the 7 bit immediate imm7 as follows imm7 0 3 0 3 bits imm7 4 7 4 bits imm7 8 or more 8 bits The sign bit is copied to the most significant bit of the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 15 rd register after execution 0 Sign bit S S S C C X X X X X X X X 0 0 0 0 0 0 0 0 23 16 2 Extension Using the ext instruction extends the 7 bit im...

Page 178: ...erformed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 3 Extension 2 ext imm3 imm3 2 0 imm16 15 13 ext imm13 imm16 12 0 sbc rd rs rd rs imm16 C The 16 bit immediate imm16 and C carry flag are subtracted from the rs register and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd r...

Page 179: ...re subtracted from the rd register after being zero extended The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext imm9 imm9 8 0 imm16 15 7 sbc rd imm7 rd rd imm16 C imm7 imm16 6 0 The 16 bit immediate imm16 and C carry flag are subtracted from the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to...

Page 180: ...r7 CLK One cycle Description 1 Standard The rd register is shifted as shown in the diagram below The number of bits to be shifted is specified by the rs register value as follows rs 0 3 0 3 bits rs 4 7 4 bits rs 8 or more 8 bits Data 0 is placed in the least significant bit of the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 0 0 15 rd registe...

Page 181: ...by the 7 bit immediate imm7 as follows imm7 0 3 0 3 bits imm7 4 7 4 bits imm7 8 or more 8 bits Data 0 is placed in the least significant bit of the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 0 0 15 rd register after execution 0 X X X X X X X X 0 0 0 0 0 0 0 0 23 16 2 Extension Using the ext instruction extends the 7 bit immediate imm7 to 20...

Page 182: ...able external interrupts NMI and debug interrupts are commonly used for canceling SLEEP mode The interrupt enable disable status set in the processor does not affect the cancellation of SLEEP mode even if an interrupt signal is used as the cancellation In other words interrupt signals are able to cancel SLEEP mode even if the IE flag in PSR or the interrupt enable bits in the interrupt controller ...

Page 183: ...r0 to r7 CLK One cycle Description 1 Standard The rd register is shifted as shown in the diagram below The number of bits to be shifted is specified by the rs register value as follows rs 0 3 0 3 bits rs 4 7 4 bits rs 8 or more 8 bits Data 0 is placed in the bit 15 of the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 0 0 15 rd register after e...

Page 184: ...cified by the 7 bit immediate imm7 as follows imm7 0 3 0 3 bits imm7 4 7 4 bits imm7 8 or more 8 bits Data 0 is placed in the bit 15 of the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 0 0 15 rd register after execution 0 C C X X X X X X X X 0 0 0 0 0 0 0 0 23 16 2 Extension Using the ext instruction extends the 7 bit immediate imm7 to 20 bit...

Page 185: ...nto the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 3 Extension 2 ext imm3 imm3 2 0 imm16 15 13 ext imm13 imm16 12 0 sub rd rs rd rs imm16 The 16 bit immediate imm16 is subtracted from the rs register and the result is loaded into the rd register The operation is performed in 16 bit size and bits...

Page 186: ...tracted from the rd register after being zero extended The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext imm9 imm9 8 0 imm16 15 7 sub rd imm7 rd rd imm16 imm7 imm16 6 0 The 16 bit immediate imm16 is subtracted from the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 3 Delayed slot instruct...

Page 187: ...esult is loaded into the rd register The content of the rs register is not altered 3 Extension 2 ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 sub a rd rs rd rs imm24 The 24 bit immediate imm24 is subtracted from the content of the rs register and the result is loaded into the rd register The content of the rs register is not altered 4 Conditional execution The c or nc suffix on the opcode...

Page 188: ...from the rd register after being zero extended 2 Extension 1 ext imm13 imm20 19 7 sub a rd imm7 rd rd imm20 imm7 imm20 6 0 The 20 bit immediate imm20 is subtracted from the rd register after being zero extended 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 sub a rd imm7 rd rd imm24 imm7 imm24 6 0 The 24 bit immediate imm24 is subtracted from the rs register 4 Delayed slot instru...

Page 189: ...ontent of the rs register after being zero extended and the result is loaded into the stack pointer SP The content of the rs register is not altered 3 Extension 2 ext imm11 imm11 10 0 imm24 23 13 ext imm13 imm24 12 0 sub a sp rs sp rs imm24 The 24 bit immediate imm24 is subtracted from the content of the rs register and the result is loaded into the stack pointer SP The content of the rs register ...

Page 190: ... 2 Extension 1 ext imm13 imm20 19 7 sub a sp imm7 sp sp imm20 imm7 imm20 6 0 The 20 bit immediate imm20 is subtracted from the stack pointer SP after being zero extended 3 Extension 2 ext imm4 imm4 3 0 imm24 23 20 ext imm13 imm24 19 7 sub a sp imm7 sp sp imm24 imm7 imm24 6 0 The 24 bit immediate imm24 is subtracted from the stack pointer SP 4 Delayed slot instruction This instruction may be execut...

Page 191: ...r direct rs r0 to r7 Dst Register direct rd r0 to r7 CLK One cycle Description 1 Standard Swaps the byte order of the 16 low order bits of the rs register high and low and loads the results to the rd register 8 7 15 Byte 0 Byte 1 0 rs 8 7 15 Byte 1 Byte 0 0 rd X X X X X X X X 23 16 0 0 0 0 0 0 0 0 23 16 2 Delayed slot instruction This instruction may be executed as a delayed slot instruction by wr...

Page 192: ...result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 The content of the rs register is not altered 3 Extension 2 ext imm3 imm3 2 0 imm16 15 13 ext imm13 imm16 12 0 xor rd rs rd rs imm16 The content of the rs register and the 16 bit immediate imm16 are exclusively OR ed and the result is loaded into the rd register The operat...

Page 193: ...ed and the result is loaded into the rd register The operation is performed in 16 bit size and bits 23 16 of the rd register are set to 0 2 Extension 1 ext imm9 imm9 8 0 sign16 15 7 xor rd sign7 rd rd sign16 sign7 sign16 6 0 The content of the rd register and the 16 bit immediate sign16 are exclusively OR ed and the result is loaded into the rd register The operation is performed in 16 bit size an...

Page 194: ...lacement imm7 Specification for a memory address with an immediate data B XXX An address specified with XXX or the byte data stored in the address W XXX A 16 bit address specified with XXX or the word data stored in the address A XXX A 32 bit address specified with XXX or the 24 bit or 32 bit data stored in the address Immediate immX A X bit unsigned immediate data signX A X bit signed immediate d...

Page 195: ...imm7 rd 23 16 0 rd 15 0 W imm7 rd 23 16 0 W rb rs 15 0 W rb rs 15 0 rb 23 0 rb 23 0 2 W rb rs 15 0 rb 23 0 rb 23 0 2 rb 23 0 rb 23 0 2 W rb rs 15 0 Cycle 1 1 2 7 2 2 2 2 1 1 2 7 2 2 2 2 1 1 1 2 7 2 2 2 2 1 1 1 1 2 7 2 2 2 2 1 1 2 7 2 2 2 EXT 1 6 6 6 5 4 1 6 6 6 5 4 1 6 6 6 5 4 2 1 6 6 6 5 4 1 6 6 6 D 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 ...

Page 196: ...sp 23 0 rs 23 0 A sp 31 24 0 sp 23 2 rs 23 2 sp 1 0 0 sp 6 2 imm7 6 2 sp 23 7 0 sp 1 0 0 Cycle 2 1 1 1 1 2 8 2 2 2 2 1 1 2 8 2 2 2 2 1 1 1 1 2 8 2 2 2 1 2 8 2 2 2 1 1 EXT 5 4 3 1 6 6 6 5 4 1 6 6 6 5 4 1 6 6 6 1 6 6 6 3 D 1 1 0 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0...

Page 197: ...d 23 0 rs 23 0 if C 0 nop if C 1 sp 23 0 sp 23 0 rs 23 0 rd 23 0 rd 23 0 imm7 zero extended sp 23 0 sp 23 0 imm7 zero extended rd 15 0 rd 15 0 rs 15 0 C rd 23 16 0 rd 15 0 rd 15 0 rs 15 0 C rd 23 16 0 if C 1 nop if C 0 rd 15 0 rd 15 0 rs 15 0 C rd 23 16 0 if C 0 nop if C 1 rd 15 0 rd 15 0 imm7 zero extended C rd 23 16 0 rd 15 0 rs 15 0 rd 15 0 rs 15 0 if C 1 nop if C 0 rd 15 0 rs 15 0 if C 0 nop i...

Page 198: ... 0 rs 15 0 rd 23 16 0 rd 15 0 rd 15 0 rs 15 0 rd 23 16 0 if C 1 nop if C 0 rd 15 0 rd 15 0 rs 15 0 rd 23 16 0 if C 0 nop if C 1 rd 15 0 rd 15 0 sign7 sign extended rd 23 16 0 rd 15 0 rd 15 0 rs 15 0 rd 23 16 0 rd 15 0 rd 15 0 rs 15 0 rd 23 16 0 if C 1 nop if C 0 rd 15 0 rd 15 0 rs 15 0 rd 23 16 0 if C 0 nop if C 1 rd 15 0 rd 15 0 sign7 sign extended rd 23 16 0 rd 15 0 rd 15 0 rs 15 0 rd 23 16 0 rd...

Page 199: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 d 0 0 0 1 1 0 0 0 0 1 1 1 1 d 0 1 0 0 1 1 0 0 0 IL IE 0 0 0 Z N C V 0 1 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 1 1 1 1 0 1 1 1 d d d d d d d d d d d d d d d d d 0 d 0 0 0 0 0 0 1...

Page 200: ...1 Code MSB LSB Mnemonic Flags Remarks 1 Number of bits to be shifted Zero to three bits when rs imm7 0 3 four bits when rs imm7 4 7 eight bits when rs imm7 8 2 With one EXT immediate imm20 With two EXT immediate imm24 Conversion Instructions S1C17 Core Instruction Set Opcode cv ab cv as cv al cv la cv ls Operand rd rs rd rs rd rs rd rs rd rs Function rd 23 8 rs 7 rd 7 0 rs 7 0 rd 23 16 rs 15 rd 15...

Page 201: ...7 co_dout0 rd co_dout1 rs rd co_din psr C V Z N co_cvzn co_dout0 rd co_dout1 imm7 rd co_din psr C V Z N co_cvzn co_dout0 rd co_dout1 rs psr C V Z N co_cvzn co_dout0 rd co_dout1 imm7 psr C V Z N co_cvzn Cycle 1 1 1 1 1 1 EXT 1 1 1 D 0 0 0 0 0 1 0 1 0 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 0 1 0 0 1 0 1 1 1 1 IL IE Z N C V 0 0 0 0 0 0 1 1 0 0 1 1 Code MSB LSB Mnemonic Flags Remarks 1 With one EXT co_dout...

Page 202: ...story Code No Page Contents 410905900 All New establishment 410905901 All Made an overall revision 410905902 6 10 Corrected the description in Canceling HALT or SLEEP mode 7 32 7 33 Added Caution to the di and ei instruction pages ...

Page 203: ...N BRANCH Room 804 805 8 Floor Tower 2 Ali Center No 3331 Keyuan South RD Shenzhen bay Nanshan District Shenzhen 518054 CHINA Phone 86 10 3299 0588 Fax 86 10 3299 0560 EPSON TAIWAN TECHNOLOGY TRADING LTD 14F No 7 Song Ren Road Taipei 110 TAIWAN Phone 886 2 8786 6688 Fax 886 2 8786 6660 EPSON SINGAPORE PTE LTD 1 HarbourFront Place 03 02 HarbourFront Tower One Singapore 098633 Phone 65 6586 5500 Fax ...

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