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Seiko Epson Corporation
S1C17 CORE MANUAL
(REV. 1.2)
ld [%sp + imm7], %rs
Function
16-bit data transfer
Standard)
W[sp +
imm7
]
←
rs
(15:0)
Extension 1) W[sp +
imm20
]
←
rs
(15:0)
Extension 2) W[sp +
imm24
]
←
rs
(15:0)
Code
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 0
r s
imm7
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Flag
IL IE C V Z N
– – – – – –
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Mode
Src: Register direct
%rs
=
%r0
to
%r7
Dst: Register indirect with displacement
CLK
Two cycles
Description
(1) Standard
ld [%sp + imm7],%rs
; memory address = sp + imm7
The 16 low-order bits of the
rs
register are transferred to the specified memory location. The
content of the current SP with the 7-bit immediate
imm7
added as displacement comprises the
memory address to be accessed.
(2) Extension 1
ext imm13
;
=
imm20(19:7)
ld [%sp + imm7],%rs
; memory address = sp + imm20,
;
imm7 = imm20(6:0)
The
ext
instruction extends the displacement to a 20-bit quantity. As a result, the 16 low-order
bits of the
rs
register are transferred to the address indicated by the content of the SP with the
20-bit immediate
imm20
added.
(3) Extension 2
ext imm4
;
imm4(3:0) = imm24(23:20)
ext imm13
;
=
imm24(19:7)
ld [%sp + imm7],%rs
; memory address = sp + imm24,
;
imm7 = imm24(6:0)
The two
ext
instructions extend the displacement to a 24-bit quantity. As a result, the 16 low-
order bits of the
rs
register are transferred to the address indicated by the content of the SP with
the 24-bit immediate
imm24
added.
(4) Delayed slot instruction
This instruction may be executed as a delayed slot instruction by writing it directly after
a branch instruction with the “d” bit. In this case, extension of the immediate by the
ext
instruction cannot be performed.
Example
ext 0x1
ld [%sp + 0x2],%r0
; W[sp + 0x82]
←
16 low-order bits of r0
Caution
The SP and the displacement must specify a 16-bit boundary address (least significant bit = 0).
Specifying an odd address causes an address misaligned interrupt. Note, however, that the data
transfer is performed by setting the least significant bit of the address to 0.