Epson Q41856470000100, Applications Manual

Page: 11 / 18

RTC - 8564 JE/NB
Page - 8 MQ - 322 - 04
8.3. Access procedure
8.3.1. Characteristic of the I
2
C-BUS
I
2
C-BUS is a bi-directional interface that uses two (2) lines. This interface has two signal lines, which are SDA (data
line) and SCL (clock line). Both of these lines are connected to the V
DD
line via the pull-up registers. All ports must be
open drain or open collector on the I
2
C-BUS in order to be able to connect multiple devices on this bus using the
AND-connection.
8.3.2. Bit transfer
The bit data transfer is executed for one bit on each one clock pulse of SCL line. When the device transmits the data,
the data change should be executed while SCL line is at LOW. When the device receives the data, the data should be
taken in while SCL is at HIGH.
8.3.3. Start condition and stop condition
When I
2
C-BUS is not interfacing, the two control lines keep at HIGH. When SDA changes from HIGH to LOW, this is
defined as a start condition. After that, actual data transfer is executed. When SCL is at HIGH and when SDA changes
from LOW to HIGH, this is defined as a stop condition.
SDA
SCL
S P
Start condition
Stop condition
8.3.4. Slave address
The I
2
C-BUS devices do not have any chip select pins with the usual logic devices. All I
2
C-BUS devices have a fixed
unique device number for each device built into them. The chip selection on the I
2
C-BUS is executed when the
communication starts and this device number is sent from I
2
C-BUS as a slave address. The receiving device responds
to the communication only if it matches the slave address.
The slave address is a 7-bit data which is made of a 4-bit fixed data (group 1) and 3-bits data (group 2). On the
RTC-8564, the data in group 1 is 1010 and in group 2 is 001.
∗
1)
RTC-8564 slave address
1 0 1 0 0 0 1
Group 1 Group 2
∗
2)
During the actual data transmission,
the transmitted data contains both the
slave address and the 8-bit data with
the added R/W (read/write) bit.
Slave address
R/W
bit
bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
1 0 1 0 0 0 1 R/W
0 ; when write mode
1 ; when read mode