Epson Q41856470000100, Applications Manual

Page: 10 / 18

RTC - 8564 JE/NB
Page - 7 MQ - 322 - 04
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C ( Century bit )
This bit indicates change of century. When the year digit data overflows from 99 to 00, this bit is set. By
presetting it to 0 while still in the 20th century, it will be set in year 2000, but in fact the first year in the 21
century should be 2001.
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Weekdays registers ( Example for allotment of a day. )
Address Function bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Week
× × × ×
0 0 0
SUN
× × × ×
0 0 1
MON
× × × ×
0 1 0
TUE
× × × ×
0 1 1
WED
× × × ×
1 0 0
THU
× × × ×
1 0 1
FRI
06 Weekdays
× × × ×
1 1 0
SAT
8.2.4. Alarm registers
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
09 Minute Alarm AE 40 20 10 8 4 2 1
0A Hour Alarm AE
×
20 10 8 4 2 1
0B Day Alarm AE
×
20 10 8 4 2 1
0C Weekday Alarm AE
× × × ×
4 2 1
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AE
This is the alarm control bit. There is an MSB for each register of minute alarm, hour alarm, day alarm, and day
of week alarm. When this bit is set to 1, the appropriate register will be set to have the alarm unconditionally
and regardless of the data, and this device is regarded as to have the circuitry working.
When the hour digit and the AE of data are set, alarm will occur at the specified minute regardless of the date
and time. In other words the alarm will occur at the specified minute of every hour. Similarly, when minute and
hour are set to AE, alarm occurs at the specified date. Therefore, by combining them in this way a highly
versatile alarm can be set. When all of the bits are set to AE, no alarm will occur.
Additional information on the alarm function:
Even when the alarm is turned on for a long time, this device clears the flag when the alarm occurs once, and
so no more further alarm will occur under the same condition. This means in the same day when the alarm
condition is met, once the alarm flag is cleared and the alarm becomes unmatched the alarm will not occur
unless new condition is met. Therefore, take note of this when using the flag.
8.2.5. CLKOUT frequency selection and timer registers
Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0D CLKOUT frequency FE
× × × × ×
FD1 FD0
0E Timer control TE
× × × × ×
TD1 TD0
0F Timer 128 64 32 16 8 4 2 1
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Frequency output
Output
frequency
FD1 FD0
32768 Hz 0 0
1024 Hz 0 1
32 Hz 1 0
1 Hz 1 1
∗
At the above setting, the output frequency of the CLKOUT pin can be
selected.
Output is possible when the FE of MSB of the D register is 1. (When
it stops, the CLKOUT pin goes to LOW.)
These output is controlled by CLKOE pin. When CLKOE input is
LOW, CLKOUT output is inhibited.
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Timer control
Timer source
clock
TD1 TD0
4096 Hz 0 0
64 Hz 0 1
1 second 1 0
1 minute 1 1
∗
At the above setting, the count down rate of the timer can be
selected.
When the TE of MSB of the E register is 1, the timer count down
starts, and stops when it becomes 0.
The F register data counts down at the set frequency and when it
becomes zero TF is set.
When the F register is read, the data during count down is read out.
•
Timer register
It sets the initial value of the timer's count down. The format is binary.