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Enclustra ME-XU1-15EG-1E-D12E-G1, User Manual

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Enclustra ME-XU1-15EG-1E-D12E-G1 User Manual Download Page 48

Pin Number

Signal Name

Description

16

TRACE_EN#

Trace interface enable signal

18

TRACE_CLK

22

TRACE_CTL

Debug trace interface

23

TRACE_DQ0

(Refer to Zynq Ult MPSoC Technical

24

TRACE_DQ4

Reference Manual [19])

25

TRACE_DQ1

26

TRACE_DQ5

27

TRACE_DQ2

28

TRACE_DQ6

29

TRACE_DQ3

30

TRACE_DQ7

Table 36: Debug Connector Interface - Revision 1 and 2 Modules

The trace signals can be used to debug the processor running at full speed, allowing the user to collect
information on the CPU instruction execution and data transfers.

In order to enable the trace interface, TRACE_EN# signal must be pulled low from the debug connector, and
MIO pins 0-9 must be assigned to TRACE controller in the PS settings of the Vivado project. Additionally,
starting with revision 2 modules, the trace clock multiplexer must be equipped. Refer to the  XU1
SoC Module User Schematics [6] for details.

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Version 13, 15.08.2019

Summary of Contents for ME-XU1-15EG-1E-D12E-G1

Page 1: ...description of its features and configuration options In addition references to other useful documents are included Product Information Code Name Product ME XU1 Mercury XU1 SoC Module Document Inform...

Page 2: ...or VCC_BAT corrected minimum MDIO clock frequency other style updates 11 08 05 2019 DIUN Corrected power synchronization frequency domain and duty cycle added information on Linux how to guide 10 05 0...

Page 3: ...Bottom Assembly Drawings 16 2 5 1 Top Assembly Drawing 16 2 5 2 Bottom Assembly Drawing 16 2 6 Module Footprint 17 2 7 Mechanical Data 17 2 8 Module Connector 18 2 9 User I O 19 2 9 1 Pinout 19 2 9 2...

Page 4: ...24 1 EEPROM Type 46 2 25 Debug Connector 46 3 Device Configuration 49 3 1 Configuration Signals 49 3 2 Module Connector C Detection 50 3 3 Pull Up During Configuration 50 3 4 Power on Reset Delay Over...

Page 5: ...5 2 Recommended Operating Conditions 62 6 Ordering and Support 63 6 1 Ordering 63 6 2 Support 63 D 0000 428 001 5 66 Version 13 15 08 2019...

Page 6: ...m and FSBL First Stage Boot Loader It downloads and compiles all required software such as U Boot Linux and BusyBox based root file system 1 1 2 Warranty Please refer to the General Business Condition...

Page 7: ...GHz Dual core ARM Cortex R5 MPCore up to 600 MHz Mali 400 MP2 GPU not for CG variants Xilinx 16nm FinFET FPGA fabric 294 user I Os 14 ARM peripheral I Os SPI SDIO CAN I2C UART 200 FPGA I Os single en...

Page 8: ...an example configuration for the Zynq Ultrascale MPSoC device together with an example top level HDL file for the user logic A number of software applications are available for the reference design th...

Page 9: ...Ethernet connectors mPCIe mSATA card holder USB only PE1 300 400 SIM card holder optional PE1 300 400 only SMA clock and data in out optional PE1 300 400 only 1 FMC LPC connector PE1 200 1 FMC HPC con...

Page 10: ...t of the Mercury XU1 SoC module is the Xilinx Zynq Ultrascale MPSoC device Most of its I O pins are connected to the Mercury module connector making up to 214 regular user I Os avail able to the user...

Page 11: ...MMC flash a 64 MB quad SPI flash and 2 GB or 4 GB DDR4 SDRAM Further the module is equipped with two Gigabit Ethernet PHYs and two USB 2 0 PHYs making it ideal for communication applications A real ti...

Page 12: ...5 C ME XU1 15EG 2I D12E XCZU15EG 2FFVC900I 4 GB 3 12 40 to 85 C ME XU1 15EG 2I D12E G1 XCZU15EG 2FFVC900I 4 GB 3 16 40 to 85 C Table 1 Standard Module Configurations Starting with revision 3 modules 4...

Page 13: ...The correspondence between article number and article code is shown in Table 2 The article code repre sents the product code followed by the revision the R suffix and number represent the revision nu...

Page 14: ...2E R4 EN102280 ME XU1 9EG 3E D12E R4 EN102281 ME XU1 15EG 2I D12E R4 EN102600 ME XU1 6CG 1E D11E G1 R4 1 EN102601 ME XU1 6CG 1E D11E R4 1 EN102614 ME XU1 6EG 1I D11E G1 R4 1 EN102372 ME XU1 6EG 1I D11...

Page 15: ...5 Module Top View 2 4 2 Bottom View Figure 6 Module Bottom View Please note that depending on the hardware revision and configuration the module may look slightly dif ferent than shown in this docume...

Page 16: ...ule Top Assembly Drawing 2 5 2 Bottom Assembly Drawing Figure 8 Module Bottom Assembly Drawing Please note that depending on the hardware revision and configuration the module may look slightly dif fe...

Page 17: ...design tools Altium PADS Eagle Orcad 8 and include the required information on the module sizes and holes The maximum component height under the module is dependent on the connector type refer to Sect...

Page 18: ...stacking heights Some examples are presented in Table 4 Please refer to the connector datasheet for more information Reference Type Description Mercury module connector FX10A 168S SV Hirose FX10 168 p...

Page 19: ...ry XU1 SoC module it may be possible that the connected pins do not have the targeted functions such as primary clocks differential pins MGT signals etc The naming convention for the user I Os is IO_B...

Page 20: ...exceptions are pins with special functions or restrictions for example when used in combination with certain Mercury boards they may have a specific role PCIe Reset Signal PERST Table 6 lists the I O...

Page 21: ...l GTH transceivers and 2 differential clock pairs may be routed to the module connector by using the G1 assembly variants This option may be useful when the user application requires 16 GTH transceive...

Page 22: ..._A27_P C 89 IO_B66_L11_GC_V7_P MGT_B128_TX3_A27_P IO_B66_L11_GC_V6_B128_TX3_A28_N C 91 IO_B66_L11_GC_V6_N MGT_B128_TX3_A28_N IO_B65_AE7_B128_REFCLK1_D25_P C 72 IO_B65_AE7_P MGT_B128_REFCLK1_D25_P IO_B...

Page 23: ...2 9 6 for details 2 9 4 I O Banks Table 9 describes the main attributes of the Programmable Logic PL and Processing System PS I O banks and indicates which peripherals are connected to each I O bank A...

Page 24: ...C_IO_B65 VCCO_65 1 0 V 1 8 V 5 64 88 140 VCC_IO_B66 VCCO_66 1 0 V4 1 8 V 5 67 95 143 VCC_IO_B47 VCCO_47 1 2 V 3 3 V 5 5 41 VCC_IO_B48 VCCO_48 1 2 V 3 3 V 5 5 38 Table 10 VCC_IO Pins 3 4 5 If the Mercu...

Page 25: ...l Figure 13 illustrates the VCC_IO power requirements Figure 13 Power Up Sequence VCC_IO in Relation with PWR_GOOD and PWR_EN Signals 2 9 6 Signal Terminations Differential Inputs Internal differentia...

Page 26: ...onnected to on board peripherals while others are available as GPIOs the suggested functions below are for reference only always verify your MIO pinout with the Xilinx device handbook Table 11 gives a...

Page 27: ...PERST signal8 Gigabit Ethernet PHY 0 and module connector via series re sistor 38 UART RX7 User functionality Module connector 39 UART TX7 40 41 43 44 User functionality Module connector 42 User func...

Page 28: ...rchitecture System Monitor document 20 Zynq UltraScale MPSoC Technical Reference Manual 19 and System Management Wizard Product Guide 22 Table 12 presents the ADC Parameters for the PL System Monitor...

Page 29: ...the MPSoC device support data rates of 12 5 Gbit sec on speedgrade 1 devices and of 16 375 Gbit sec on the other devices Note that the maximum bandwidth is limited to 15 Gbit sec by the module connec...

Page 30: ...performance rates Warning No AC coupling capacitors are placed on the Mercury XU1 SoC module on the MGT lines make sure capacitors are mounted if required on the base board close to the module pins to...

Page 31: ...ercury XU1 SoC Module Known Issues and Changes document 7 for details Please refer to the Enclustra Module Pin Connection Guidelines for general rules on the power pins 11 Power Converter Synchronizat...

Page 32: ...00 kHz Depending on the selected frequency it is recommended to adjust the duty cycle of the synchronization clock accordingly in order to ensure a minimum time of 600 ns for the high level of the clo...

Page 33: ...11 3 Voltage Supply Inputs Table 17 describes the power supply inputs on the Mercury XU1 SoC module The VCC voltages used as supplies for the I O banks are described in Section 2 9 5 Pin Name Module C...

Page 34: ...like the Xilinx Zynq Ultrascale MPSoC need cooling in most applications always make sure the MPSoC is adequately cooled Table 19 lists the heat sink and thermal pad part numbers that are compatible w...

Page 35: ...ector Pin Connection Description VMON_INT A 102 VCC_INT PL core voltage VMON_1V2_VBAT B 8 VCC_1V2 1 2 V on board voltage default MPSoC battery voltage assembly option VMON_PSINT C 8 VCC_PSINT PS core...

Page 36: ...d from an external SPI master For details on the functions of the PS_POR_B and PS_SRST_B signals refer to the Zynq UltraScale MPSoC Technical Reference Manual 19 Table 22 presents the available reset...

Page 37: ...DDR4 SDRAM channel on the Mercury XU1 SoC module attached directly to the PS side and is available only as a shared resource to the PL side The DDR4 SDRAM is connected to PS I O bank 504 The memory co...

Page 38: ...RAM memory may be equipped on the module 2 15 2 Signal Description Please refer to the Mercury XU1 SoC Module FPGA Pinout Excel Sheet 4 for detailed information on the DDR4 SDRAM connections 2 15 3 Te...

Page 39: ...ncy 0 RAS to CAS delay 17 Precharge time 17 tRC 46 16 ns tRASmin 32 ns tFAW 30 ns Table 26 DDR4 SDRAM Parameters 2 16 QSPI Flash The QSPI flash can be used to boot the PS and to store the FPGA bitstre...

Page 40: ...Configuration The QSPI flash supports up to 50 MHz operation for standard read For fast dual and quad read speed values please refer to the flash device datasheet Note that the Feedback Clk option on...

Page 41: ...k pull up resistor to 1 8 V and the data lines have 47 k pull up resistors to 1 8 V 2 18 SD Card An SD card can be connected to the PS MIO pins 45 51 The corresponding MIO pins are available on the m...

Page 42: ...n is enabled Warning Gigabit Ethernet 1 interface is not available when USB 1 interface is active USB1_RST _ETH1_RST is pulled to GND via a 1 k resistor to release the USB PHY from reset this signal m...

Page 43: ...thernet PHYs are set as indicated in Table 31 Pin Signal Value Description MODE 3 0 1110 RGMII mode advertise all capabilities 10 100 1000 half full duplex ex cept 1000Base T half duplex PHYAD 2 0 011...

Page 44: ...cription The ULPI interface for the PHY 0 is connected to MIO pins 52 63 for use with the integrated USB controller The ULPI interface for the PHY 1 is connected to MIO pins 64 75 The MIO signals are...

Page 45: ...and the USB 2 0 signals from the PHY all routed to a USB 3 0 connector on the base board Figure 14 USB 3 0 Implementation Example Warning The USB 3 0 interface on the Mercury XU1 SoC module uses the G...

Page 46: ...et MAC address and other information It is connected to the I2C bus The secure EEPROM must not be used to store user data Please refer to Section 4 4 for details on the content of the EEPROM 2 24 1 EE...

Page 47: ...NT _PJTAG_TCK PJTAG TCK 7 EMMC_IO0_JTAG_TDI PJTAG TDI 9 EMMC_IO1_PJTAG_TDO PJTAG TDO 2 PJTAG_EN PJTAG enable enable PJTAG boot mode 5 20 31 32 33 34 GND Ground 10 VCC_3V3 11 VCC_CFG_MIO 21 VCC_ 1V8 4...

Page 48: ...ace signals can be used to debug the processor running at full speed allowing the user to collect information on the CPU instruction execution and data transfers In order to enable the trace interface...

Page 49: ...nal master Please refer to Section 3 12 for details Signal MPSoC Mod Conn Name Pin Type Pin Description Comments FLASH_CLK MIO0 A 118 SPI CLK 10 k pull up to VCC_CFG_MIO FLASH_DO MIO1 A 122 SPI MISO F...

Page 50: ...4 7 k pull up resistor on the module 3 3 Pull Up During Configuration The Pull Up During Configuration signal PUDC is pulled to GND on the module as PUDC is an active low signal all FPGA I Os will ha...

Page 51: ...om view drawing For details on the POR_OVERRIDE signal please refer to the Zynq UltraScale MPSoC Technical Reference Manual 19 3 5 Boot Mode The boot mode can be selected via two signals available on...

Page 52: ...tem test and debug are available in the Zynq UltraScale MPSoC Technical Ref erence Manual 19 On modules equipped with ES1 engineering samples 1 MPSoC devices PJTAG boot mode is required in order to pr...

Page 53: ...Signal Name Pin on Debug Connector PS Pin Resistor I2C_INT _PJTAG_TCK 3 MIO12 51 7 k pull up to VCC_3V3 EMMC_IO2_PJTAG_TMS 1 MIO15 47 k pull up to VCC_1V8 EMMC_IO0_PJTAG_TDI 7 MIO13 47 k pull up to V...

Page 54: ...flash device is connected to the PS MIO pins 0 5 3 9 SD Card Boot Mode In the SD card boot mode the PS boots from the SD card located on the base board There are two SD card boot modes available on t...

Page 55: ...ertain Xilinx tools versions support QSPI flash programming via JTAG only when JTAG boot mode is used unavailable in the standard configurations of the Mercury XU1 SoC module For more information plea...

Page 56: ...a base board the QSPI flash can be programmed using Enclustra Module Configuration Tool MCT 17 For this method a non QSPI boot mode must be used during QSPI flash programming The entire procedure is d...

Page 57: ...ls must be connected to open collector outputs and must not be driven high from any source I2C_INT is an input to the MPSoC and must not be driven from the MPSoC device Starting with revision 2 module...

Page 58: ...EEPROM is for Enclustra use only Any attempt to write data to the secure EEPROM causes the warranty to be rendered void 4 4 1 Memory Map Address Length bits Description 0x00 32 Module serial number 0x...

Page 59: ...count 0 2 0x0B 7 4 DDR4 ECC RAM size GB 0 0 GB 4 8 GB Resolution 1 GB 3 0 QSPI flash memory size MB 0 0 MB 7 64 MB Resolution 1 MB 0x0C 7 4 eMMC flash size GB 0 0 GB 5 16 GB Resolution 1 GB 3 0 Reser...

Page 60: ...s Value Module Temperature Range 0 Commercial 1 Extended 2 Industrial Table 48 Module Temperature Range Ethernet MAC Address The Ethernet MAC address is stored using big endian byte order MSB on the l...

Page 61: ...e for MPSoC battery backed RAM and battery backed RTC 0 to 3 6 V VCC_IO_B47 Output drivers supply voltage relative to GND 0 5 to 3 4 V VCC_IO_B48 VCC_CFG_MIO Output drivers supply voltage relative to...

Page 62: ...battery backed RTC 2 7 to 3 6 V VCC_IO_ x Output drivers supply voltage relative to GND Refer to V VCC_CFG_ x Section 2 9 5 V_IO I O input voltage relative to GND 0 2 to VCCO 0 2 V Temperature Temper...

Page 63: ...tra online request order form for ordering or requesting information http www enclustra com en order 6 2 Support Please follow the instructions on the Enclustra online support site http www enclustra...

Page 64: ...vision 4 Modules 54 18 QSPI Flash Programming from an External SPI Master Signal Diagrams 56 List of Tables 1 Standard Module Configurations 12 2 Article Numbers and Article Codes 14 3 Mechanical Data...

Page 65: ...and PS Access and Debug 53 40 JTAG Interface ARM DAP Access via PJTAG Signals valid only for modules revision 1 and 2 53 41 SD Card Boot Modes 55 42 I2C Signal Description 57 43 I2C Addresses 58 44 EE...

Page 66: ...hirose connectors com 14 Mercury PE1 User Manual Ask Enclustra for details 15 Enclustra Build Environment Ask Enclustra for details 16 Enclustra Build Environment How To Guide Ask Enclustra for detai...

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