Warning!
Do not use excessive force to latch a Mercury module into the Mercury connectors on the base board,
as this could damage the module and the base board; always make sure that the module is correctly
oriented before mounting it into the base board.
2.9
User I/O
2.9.1
Pinout
Information on the XU1 SoC module pinout can be found in the Enclustra Mercury Master Pinout
[12], and in the additional document Enclustra Module Pin Connection Guidelines [11].
Warning!
Please note that the pin types on the schematics symbol of the module connector and in the Master
Pinout document are for reference only. On the XU1 SoC module it may be possible that
the connected pins do not have the targeted functions (such as primary clocks, differential pins, MGT
signals, etc).
The naming convention for the user I/Os is:
IO_B<BANK>_L<PAIR><_SPECIAL_FUNCTION>_<PACKAGE_PIN>_<POLARITY>.
For example, IO_B64_L18_AD2_AH4_P is located on pin AH4 of I/O bank 64, pair 18, it is a System Monitor
differential auxiliary analog input capable pin and it has positive polarity, when used in a differential pair.
The global clock capable pins are marked with “GC” (HP I/O banks) or with “HDGC” (HD I/O banks) in the
signal name. For details on their function and usage, please refer to the Xilinx documentation.
Table 5 includes information related to the total number of I/Os available in each I/O bank and possible
limitations.
D-0000-428-001
19 / 66
Version 13, 15.08.2019
