2
Module Description
2.1
Block Diagram
Figure 1: Hardware Block Diagram
Figure 2: Hardware Block Diagram - G1 Variants
The main component of the XU1 SoC module is the Xilinx Zynq Ult MPSoC device. Most
of its I/O pins are connected to the module connector, making up to 214 regular user I/Os avail-
able to the user. Further, up to twenty MGT pairs are available on the module connector, making possible the
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Version 13, 15.08.2019
