Emulex MD21/S2, Technical Manual

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SCSI Bus Interface
HANDSHAKE
Note: All Signals
Shown Active Low
(Busy)
(Select)
(Control/Data)
(Input/Output)
■ (Request)
(Acknowledge)
(Attention)
(Message)
(Reset)
-REQ
-ACK ■
-ATN .
-MSG '
-RST
(Data bit) DB(7-0,P)
BUS
DB(7) ( = significant bit. | FREE
'
'
V=
Highest priority ID for arbitration PHASE
r— BUS SET DELAY Maximum time for an SCSI device to assert BSY and
its SCSI ID bit on the data bus after it detects Bus Free Phase.
BUS FREE DELAY Minimum time that an SCSI device shall wait from its
detection of Bus Free Phase until its assertion of BSY.
BUS CLEAR DELAY Maximum time for an SCSI device to stop driving all
bus signals after Bus Free Phase is detected or SEL
received from an SCSI device during arbitration.
ARBITRATION Minimum time an SCSI device shall wait from
DELAY
asserting BSY for arbitration until the data bus can be
examined to see if arbitration has been won.
BUS SETTLE DELAY Time to wait for the bus to settle after changing
Initiator asserts BSY
“V
Note:
DB(P) = Data parity (odd).
Parity is not valid
during arbitration.
The use of parity is a
system option.
Note:
In a typical system, a com pu­
ter's host adapter will act as
the Initiator and an I/O
device’s control unit will act
as the Target.
SEL and
BSY are
both false
for at least
one Bus
Settle
Delay.
Arbitration ID’S
Initiator tries
to get bus
-ARBITRATION .
■
PHASE •
r
L
Implementation of
.this phase is a
system option.
At least one Bus
Free Delay, but no
more than one Bus
Set Delay, after Bus
Free Phase has
been detected. The
Initiator asserts BSY
and its own SCSI
device ID bit on the
data bus.
The Initiator waits
an Arbitration Delay
then examines the
data bus. If a higher
priority SCSI device
ID bit is true on the
data bus (DB7 is the
highest), the Initiator
loses arbitration and
releases BSY. If no
higher priority SCSI
device ID bit is true
on the data bus,
then the Initiator
wins arbitration and
asserts SEL.
Bus devices having
lost arbitration, shall
release BSY and
their own SCSI
device ID bit within
a Bus Clear Delay
after SEL becomes
true.
The Initiator that
wins arbitration
waits at least a Bus
Clear Delay plus a
Bus Settle Delay
after asserting SEL
before changing any
signals on the bus.
> 4
Li
certain control signals.
— — *4— 2 deskew delays
-Systems with
no arbitration
start here
X
Targe
■4— 1-
I I
In itia to rlD ^ T a rg e H D ^
Initiator has bus
and selects Target.
SELECTION
PHASE
l~
r
During this phase, the
I/O signal is
deasserted to
distinguish this phase
from the Reselection
Phase.
NON-ARBITRATING
SYSTEMS: In systems
with the Arbitration
Phase not
implemented, after
detecting the Bus Free
Phase, the Initiator
waits a minimum of
one Bus Clear Delay,
then it asserts the data
bus with both the
desired Initiator ID bit
and the Target's ID bit.
After two deskew
delays, the Initiator
asserts SEL.
ARBITRATING
SYSTEMS: In systems
with the Arbitration
Phase implemented,
the Initiator that won
arbitration has both
BSY and SEL asserted
and changes the data
bus after two Bus
Settle Delays. The
data bus is then
asserted with both the
desired Initiator ID bit
and the Target’s ID bit.
Two deskew delays
later BSY is released.
IN ALL SYSTEMS: The
Target determines that
it is selected when
SEL and its SCSI
device ID bit are true
and BSY and I/O are
false for at least a Bus
Settle Delay. The
Target then asserts
BSY within a Selection
Abort Time.
Two deskew delays
after the Initiator
detects BSY true, it
releases SEL and may
change data bus
signals.
r
“■
y- '
-<H
H
H
H
H
-f H
-JH
-* H
- f H
Figure 7-3. SCSI Bus Timing Diagram (Sheet 1 of 3)
MD2103-0588A
7-10 Interfaces