Emulex MD21/S2, Technical Manual

Page: 70 / 88

SCSI Bus Interface
(Busy)
(Select)
(Control/Data)
(In pu t/Output)
(Request)
(Acknowledge)
(Attention)
(Message)
(Reset)
(Data bit)
Figure
-BSV $-
- "Deskew delay" (45 ns)
I
is____
-SEL H
C/D f —-- V
1 . v — V
v
—
i
i
i
i
1 II
i
1
i
* II i/
\
i
i
i
i
i I
i
1
\\
_
V
1
ms____
/ i
i
i
11 !
1 1
i n
i
i
i ii
^— !
— i
m \
i i
___ LU_! __II ____
1
I I I ! !
1 1
i n
l i
ii
i __
y
—
i
i
i
ii
i i i n i
i
i
i
i il l 1 1 I l l ' l l i l
1 \ v g l l d _ / |
| ^ Status byte |
| \ valid 7
I
* Message byte
1
1
— i--------------r u r r
1 Bus is 1
I Target .
1
Target "requests"! I released 1
! “ requests" 1
I
1 Initiator to |
1 take status |
1......- STATUS -------1
' message .
t z z MESSAGE 3 Z J
1 I
t BUS
| PHASE -------
I I------ PHASE ------ 1 f z : FREE * i
. (Ending
' Status) 1
. (Interrupt)
1
|
, PHASE 1
j
p Target
p Target
'
requests
|
[-Target 1
1 deasserts BSY |
. requests that a 1
1 status byte be |
1 message
1
1 to indicate that i
| sent to the |
1 byte(s) to be 1 | the bus is .
■ Initiator. ,
j sent from
1
I available for '
1 1
| Target to
1
subsequent |
L Target asserts 1
I Initiator.
|
1 users. j
1 C/D and I/O |
| and deasserts |
| MSG during .
I— Target asserts
I
C/D, I/O and
1
1
pTa rge t releases
1
all bus signals 1
. the handshake
'
MSG during
1 1
within
a
Bus |
' of this phase. '
1 the REQ/ACK
1
1 Clear Delay ■
1 handshake(s)
|
| after BSY
Only one byte |
1 of this phase.
|
I becomes
■
of status is |
1
I
I continuously
1
, transferred. i
f—
The message
; false for a Bus |
1 1 j
byte could
I
1
Settle Delay.
1-
See handshake
1
indicate 1
1 |
| procedure 1
COMMAND
1
[-T h e following .
i under Data In 1
COMPLETE
|
■ phase will be
'
| phase. 1
1 |
j (00) indicating
j
an Arbitration 1
interrupt.
1
Phase if
1
1 implemented or 1
1
1—
See handshake
1 | a
Selection
1
! i
| procedure
j under Data In
■ phase.
1
1
1
j
Phase.
|
MD2103-0588C
7-3. SCSI Bus Timing Diagram (Sheet 3 of 3)
7-12 Interfaces