MVME51005E Single Board Computer Installation and Use (6806800A38B)
7 Programming the MVME5100
74
Default Processor Memory Map
The default processor memory map that is valid at power-up or reset remains in effect until
reprogrammed for specific applications.
Table 7-1
defines the entire default map ($00000000
to $FFFFFFFF).
Note
The first 1MB of ROM/FLASH Bank A (soldered Flash up to 8MB) appears in this range
after a reset if the
rom_b_rv
control bit in the SMC’s ROM B Base/Size register is
cleared. If the
rom_b_rv
control bit is set, this address range maps to ROM/FLASH
Bank B (socketed 1MB Flash).
For an example of the CHRP memory map, refer to the following table. For detailed processor
memory maps, including suggested CHRP- and PREP-compatible memory maps, refer to the
MVME5100-Series Single Board Computer Programmer’s Reference Guide
.
Table 7-1. Default Processor Memory Map
Processor Address
Size
Definition
Start
End
0000 0000
7FFF FFFF
2GB
Not Mapped
8000 0000
8080 FFFF
8M+64K
Zero-based PCI/ISA I/O Space
8081 0000
FEF7 FFFF
2GB-24MB-576KB
Not Mapped
FEF8 0000
FEF8 FFFF
64KB
System Memory Controller
Registers
FEF9 0000
FEFE FFFF
384KB
Not Mapped
FEFF 0000
FEFF FFFF
64KB
PCI Host Bridge (PHB) Registers
FF00 0000
FFEF FFFF
15MB
Not Mapped
FFF0 0000
FFFF FFFF
1MB
ROM/FLASH Bank A or Bank B
(See Not
e)