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6 Pin Assignments

MVME51005E Single Board Computer Installation and Use (6806800A38B)

57

Note

PIN 130, 131, MEZZ1_L, MEZZ2_L, configures the board’s local bus frequency. If a
single mezzanine is attached to the board, MEZZ1_L will be pulled down on the board.
If a second mezzanine is attached on-top to the first, MEZZ2_L will be pulled down on
the board. This may cause the clock generation logic to set the local bus frequency to
83.33 MHz if necessary.

PCI Expansion Connector (J25) Pin Assignments

This connector is used to provide PCI/PMC expansion capability. The pin assignments for this
connector are as follows:

97

A10

A09

98

99

GND

GND

100

101

A08

A07

102

103

A06

A05

104

105

A04

A03

106

107

A02

A01

108

109

+3.3V

+3.3V

110

111

A00

CS_C0_L

112

113

CS_E0_L

GND

114

115

CS_C1_L

CS_E1_L

116

117

WE_L

RAS_L

118

119

GND

GND

120

121

CAS_L

+3.3V

122

123

+3.3V

DQMB0

124

125

DQMB1

SCL

126

127

SDA

A1_SPD

128

129

A0_SPD

MEZZ1_L

130

131

MEZZ2_L

GND

132

133

GND

SDRAMCLK1

134

135

SDRAMCLK3

+3.3V

136

137

SDRAMCLK4

SDRAMCLK2

138

139

GND

GND

140

Table 6-2. Memory Expansion Connector Pin Assignments (continued)

Pin

Assignment

Pin

«
...
73
74
75
76
77
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»

Summary of Contents for MVME51005E

Page 1: ...i MVME51005E Single Board Computer Installation and Use 6806800A38B August 2008 Edition ...

Page 2: ...ocument as a URL to a Emerson website The text itself may not be published commercially in print or electronic form edited translated or otherwise altered without the permission of Emerson It is possible that this publication may contain reference to or information about Emerson products machines and programs programming or services that are not available in your country Such references or informa...

Page 3: ...ide the Equipment Operating personnel must not remove equipment covers Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Service personnel should not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the po...

Page 4: ...l lithium batteries Caution Danger of explosion if battery is replaced incorrectly Replace battery only with the same or equivalent type recommended by the equipment manufacturer Dispose of used batteries according to the manufacturer s instructions Attention Il y a danger d explosion s il y a remplacement incorrect de la batterie Remplacer uniquement avec une batterie du même type ou d un type éq...

Page 5: ...nication network equipment Electromagnetic compatibility EMC requirements System products also fulfill EN60950 product safety which is essentially the requirement for the Low Voltage Directive 73 23 EEC Board products are tested in a representative system to show compliance with the above mentioned requirements A proper installation in a CE marked system will maintain the required EMC safety perfo...

Page 6: ......

Page 7: ...g Instructions 2 Preparation 3 Hardware Configuration 3 Jumper Settings 4 PMC SBC 761 IPMC Mode Selection 5 Installation Considerations 5 Installation 6 PMC Modules 7 Primary PMCspan 8 Secondary PMCspan 9 MVME5100 11 2 Operation 13 Introduction 13 Switches and Indicators 13 ABT RST Switch 13 Abort Function 13 Reset Function 13 Status Indicators 14 RST Indicator DS1 14 CPU Indicator DS2 14 Connecto...

Page 8: ...ommand Buffer 30 Standard Commands 31 Diagnostics 34 4 Functional Description 37 Introduction 37 Features Summary 37 Features Descriptions 38 General 38 Processor 39 System Memory Controller and PCI Host Bridge 40 Memory 40 Flash Memory 40 ECC SDRAM Memory 41 P2 Input Output I O Modes 41 Input Output Interfaces 41 Ethernet Interface 41 VMEbus Interface 42 Asynchronous Communications 42 Real Time C...

Page 9: ...60 VMEbus Connectors P1 P2 Pin Assignments PMC mode 68 VMEbus P1 P2 Connector Pin Assignments SBC Mode 69 10 BaseT 100 BaseTx Connector Pin Assignments 71 COM1 and COM2 Connector Pin Assignments 72 7 Programming the MVME5100 73 Introduction 73 Memory Maps 73 Processor Bus Memory Map 73 Default Processor Memory Map 74 Processor Memory Map 75 PCI Memory Map 76 VME Memory Map 76 PCI Local Bus Memory ...

Page 10: ...5 C Thermal Analysis 89 Thermally Significant Components 89 Component Temperature Measurement 92 Preparation 92 Measuring Junction Temperature 93 Measuring Case Temperature 93 Measuring Local Air Temperature 94 D Related Documentation 97 Emerson Network Power Embedded Computing Documents 97 Manufacturers Documents 98 Related Specifications 99 ...

Page 11: ...pan16E 002 10 Figure 2 1 Boot Up Sequence 15 Figure 4 1 MVME5100 Block Diagram 39 Figure 5 1 RAM500 Block Diagram 45 Figure 5 2 RAM500 Module Placement on MVME5100 46 Figure 7 1 VMEbus Master Mapping 78 Figure 7 2 MVME5100 Interrupt Architecture 79 Figure C 1 Thermally Significant Components on the MVME5100 SBC Primary Side 91 Figure C 2 Thermally Significant Components on the IPMC761 Module Prima...

Page 12: ......

Page 13: ... Table 6 5 PMC Slot 1 Connector J12 Pin Assignments 62 Table 6 6 PMC Slot 1 Connector J14 Pin Assignments 64 Table 6 7 Pin Assignments for Connector P2 in PMC Mode 68 Table 7 1 Default Processor Memory Map 74 Table 7 2 Suggested CHRP Memory Map 75 Table 7 3 Hawk PPC Register Values for Suggested Memory Map 76 Table 7 4 PCI Arbitration Assignments 78 Table 7 5 Devices Affected by Various Resets 81 ...

Page 14: ......

Page 15: ...z MPC7410 512MB ECC SDRAM 17MB Flash and 2MB L2 cache MVME51105E 226x 500 MHz MPC7410 512MB ECC SDRAM 17MB Flash and 2MB L2 cache MVME712M Compatible I O IPMC7126E 002 Multifunction rear I O PMC module 8 bit SCSI Ultra Wide SCSI one parallel port three async and one sync async serial port MVME712M6E Transition module connectors One DB 25 sync async serial port three DB 25 async serial ports one AU...

Page 16: ...ting of the basic commands are also provided Chapter 4 Functional Description provides a summary of the MVME5100 features a block diagram and a description of the major functional areas Chapter 5 RAM500 Memory Expansion Module provides a description of the RAM500 Memory Expansion Module a list of features a block diagram of the module a table of memory size allocations an installation procedure an...

Page 17: ...vendor documentation and industry related specifications Comments and Suggestions We welcome and appreciate your comments on our documentation We want to know what you think about our manuals and how we can make them better Mail comments to us by filling out the following online form http www emersonnetworkpowerembeddedcomputing com Contact Us Online Form In Area of Interest select Technical Docum...

Page 18: ...ted by that signal occur on high to low transition In this manual assertion and negation are used to specify forcing a signal to a particular state In particular assertion and assert refer to a signal that is active or true negation and negate indicate a signal that is inactive or false These terms are used independently of the voltage level high or low that they represent Data and address sizes a...

Page 19: ...onfigurable by setting on board jumpers Two I O modes are possible PMC mode or SBC mode also called 761 or IPMC mode The SBC mode uses the IPMC712 I O PMC and the MVME712M Transiton Module or the IPMC761 I O PMC and the MVME761 Transition Module The SBC mode is backwards compatible with the MVME761 transition card and the P2 adapter card excluding PMC I O routing used on the MVME2600 2700 product ...

Page 20: ...m pad when installing or upgrading a system Electronic components such as disk drives computer boards and memory modules can be extremely sensitive to electrostatic discharge ESD After removing the component from its protective wrapper or from the system place the component on a grounded static free and adequately protected working surface Do not slide the component over any surface In the case of...

Page 21: ...guration For additional information on the board s control registers refer to the MVME5100 Single Board Computer Programmer s Reference Guide listed in Appendix D Related Documentation It is important to note that some options are not software programmable These specific options are controlled through manual installation or removal of jumpers and in some cases the addition of other interface modul...

Page 22: ... J4 J6 J10 J17 and J20 These are factory configured for the PMC mode Verify all settings according to the previous table and follow the instructions below if applicable J7 Flash Memory Selection Pins 1 2 for Soldered Bank A Sockete d Bank B Pins 2 3 for Socketed Bank B J10 J17 Ethernet Port 2 Selection see also J4 For Front Panel Ethernet Port 2 Pins 1 3 and 2 4 on Both Jumpers Front Panel Etherne...

Page 23: ...The MVME5100 will not function properly without its main board connected to VMEbus backplane connectors P1 and P2 Whether the MVME5100 operates as a VMEbus master or as a VMEbus slave it is configured for 32 bits of address and 32 bits of data A32 D32 However it handles A16 or A24 devices in the appropriate address ranges D8 and or D16 devices in the system must be handled by the processor softwar...

Page 24: ...If you have ordered one or more of the optional RAM500 memory mezzanine boards for the MVME5100 ensure that they are installed on the board prior to proceeding If they have not been installed by the factory and you are installing them yourself please refer to Chapter 5 RAM500 Memory Expansion Module for installation instructions It is recommended that the memory mezzainine modules be installed pri...

Page 25: ...al ground Note that the system chassis may not be grounded if it is unplugged The ESD strap must be secured to your wrist and to ground throughout the procedure 2 Perform an operating system shutdown Turn the AC or DC power off and remove the AC cord or DC power lines from the system Remove chassis or system cover s as necessary for access to the VME modules 3 If the MVME5100 has already been inst...

Page 26: ...ou have read the user s manual that was furnished with your PMCspan and that you have installed the selected PMC modules on to your PMCspan according to the instructions provided in the PMCspan and PMC manuals 1 Attach an ESD strap to your wrist Attach the other end of the ESD strap to an electrical ground Note that the system chassis may not be grounded if it is unplugged The ESD strap must be se...

Page 27: ...with MVME5100 connector J25 Figure 1 4 PMCspan 002 Installation on an MVME5100 6 Gently press the PMCspan and MVME5100 together and verify that P4 is fully seated in J25 7 Insert four short screws Phillips type through the holes at the corners of the PMCspan and into the standoffs on the MVME5100 Tighten screws securely Secondary PMCspan The PMCspan16E 010 PCI expansion module mounts on top of a P...

Page 28: ...e instructions provided in the PMCspan and PMC manuals Figure 1 5 PMCspan16E 010 Installation on a PMCspan16E 002 1 Attach an ESD strap to your wrist Attach the other end of the ESD strap to an electrical ground Note that the system chassis may not be grounded if it is unplugged The ESD strap must be secured to your wrist and to ground throughout the procedure 2 Perform an operating system shutdow...

Page 29: ...form the following steps to install the MVME5100 in your VME chassis Warning Dangerous voltages capable of causing death are present in this equipment Use extreme caution when handling testing and adjusting Caution Inserting or removing modules with power applied may result in damage to module components Avoid touching areas of integrated circuitry static discharge can damage these circuits 1 Atta...

Page 30: ... have an auto jumpering feature for automatic propagation of the IACK and BG signals The step immediately below does not apply to such backplane designs 6 On the chassis backplane remove the INTERRUPT ACKNOWLEDGE IACK and BUS GRANT BG jumpers from the header for the card slots occupied by the MVME5100 and any PMCspan modules 7 If you intend to use PPCbug interactively connect the terminal that is ...

Page 31: ...led to ABT the switch generates an interrupt signal to the processor The interrupt is normally used to abort program execution and return control to the debugger firmware located in the processor and flash memory The interrupt signal reaches the processor via ISA bus interrupt line IRQ8 The interrupter connected to the ABORT switch is an edge sensitive circuit filtered to remove switch bounce Rese...

Page 32: ...VME5100 Two are bottom labeled 10 100BASE T and one is labeled DEBUG 10 100BASE T Ports The two RJ 45 ports labeled 10 100BASE T provide the 10BASE T 100BASE TX Ethernet LAN interface These connectors are top labeled with the designation LAN1 and LAN2 DEBUG Port The RJ 45 port labeled DEBUG provides an RS232 serial communications interface based on TL16C550 Universal Asynchronous Receiver Transmit...

Page 33: ...d specific application there may or may not be a need to modify the firmware configuration before you boot the operating system If it is necessary refer to Chapter 3 PPCBug Firmware for additional information on modifying firmware default parameters The following flowchart in Figure 2 1 shows the basic initialization process that takes place during MVME5100 system start ups For further information...

Page 34: ......

Page 35: ...r system evaluation The PPCBug provides a high degree of functionality user friendliness portability and ease of maintenance The PPCBug also achieves its portability because it was written entirely in the C programming language except where necessary to use assembler functions PPCBug includes commands for Display and modification of memory Breakpoint and tracing capabilities A powerful assembler a...

Page 36: ...is checksummed at every power on or reset firmware entry The result which includes a precalculated checksum contained in the flash devices is verified against the expected checksum PPCBug requires a maximum of 768KB of read write memory The debugger allocates this space from the top of memory For example a system containing 64MB 0x04000000 of read write memory will place the PPCBug memory location...

Page 37: ...ware Initialization The debugger performs the hardware and firmware initialization process This process occurs each time the MVME5100 is reset or powered up The steps listed below are a high level outline be aware that not all of the detailed steps are listed 1 Sets MPU MSR to known value 2 Invalidates the MPU s data instruction caches 3 Clears all segment registers of the MPU 4 Clears all block a...

Page 38: ...ge if the verification fails 29 Probes PCI bus for supported network devices 30 Probes PCI bus for supported mass storage devices 31 Initializes the memory IO addresses for the supported PCI bus devices 32 Executes Self Test if so configured Default is no Self Test 33 Extinguishes the board fail LED if Self Test passed and outputs any warning messages 34 Executes boot program if so configured Defa...

Page 39: ...Reference Guide listed in Appendix D Related Documentation Listed and described below are the parameters that you can configure using ENV The default values shown were those in effect when this publication went to print Configuring the PPCBug Parameters The parameters that can be configured using ENV are Bug or System environment B S B Maximum Memory Usage MB 0 AUTO 1 This parameter specifies the ...

Page 40: ...the cross loaded program Probe System for Supported I O Controllers Y N Y Auto Initialize of NVRAM Header Enable Y N Y Y Display the field service menu N Do not display the field service menu Default G Use the Global Control and Status Register to pass and start execution of the cross loaded program M Use the Multiprocessor Control Register MPCR in shared RAM to pass and start execution of the cro...

Page 41: ...rk booting same boot image from a network interface as from a mass storage device N Do not enable PReP style network booting Default Y Negate the VMEbus SYSFAIL signal during board initialization N Negate the VMEbus SYSFAIL signal after successful completion or entrance into the bug command monitor Default Y Local SCSI bus is reset on debugger setup N Local SCSI bus is not reset on debugger setup ...

Page 42: ... the PPCBug Firmware Package User s Manual listed in Appendix D Related Documentation for a listing of disk tape devices currently supported by PPCBug Default 0x00 Auto Boot Partition Number 00 Identifies which disk partition is to be booted as specified in the PowerPC Reference Platform PReP specification If set to zero the firmware will search the partitions in order 1 2 3 4 until it finds the f...

Page 43: ...quence will delay before starting the boot The purpose for the delay is to allow you the option of stopping the boot by use of the BREAK key The time value is from 0 255 seconds Default 5 seconds ROM Boot Direct Starting Address FFF00000 The first location tested when PPCBug searches for a ROMboot module Default 0xFFF00000 ROM Boot Direct Ending Address FFFFFFFC The last location tested when PPCBu...

Page 44: ...on parameters are to be saved retained in NVRAM these parameters are the necessary parameters to perform an unattended network boot A typical offset might be 0x1000 but this value is application specific Default 0x00001000 Caution If you use the NIOT debugger command these parameters need to be saved somewhere in the offset range 0x00001000 through 0x000016F7 The NIOT parameters do not exceed 128 ...

Page 45: ...ache Parity Enable On Detection Always Never O A N O PCI Interrupts Route Control Registers PIRQ0 1 2 3 0A0B0E0F Initializes the PIRQx PCI Interrupts route control registers in the IBC PCI ISA bus bridge controller The ENV parameter is a 32 bit value that is divided by 4 fields to specify the values for route control registers PIRQ0 1 2 3 The default is determined by system type as shown PIRQ0 0A ...

Page 46: ... Control 00000000 The configured value is written into the LSI0_CTL register of the Universe chip PCI Slave Image 0 Base Address Register 00000000 The configured value is written into the LSI0_BS register of the Universe chip PCI Slave Image 0 Bound Address Register 00000000 The configured value is written into the LSI0_BD register of the Universe chip PCI Slave Image 0 Translation Offset 00000000...

Page 47: ...chip VMEbus Slave Image 0 Base Address Register 00000000 The configured value is written into the VSI0_BS register of the Universe chip VMEbus Slave Image 0 Bound Address Register Local DRAM Size The configured value is written into the VSI0_BD register of the Universe chip The value is the same as the Local Memory Found number already displayed VMEbus Slave Image 0 Translation Offset 00000000 The...

Page 48: ... Miscellaneous Register 10000000 The configured value is written into the LMISC register of the Universe chip Special PCI Slave Image Register 00000000 The configured value is written into the SLSI register of the Universe chip Master Control Register 80C00000 The configured value is written into the MAST_CTL register of the Universe chip Miscellaneous Control Register 52060000 The configured valu...

Page 49: ...f commands with changes must be reentered Standard Commands The individual debugger commands are listed in the following table The commands are described in detail in the PPCBug Firmware Package User s Manual listed in Appendix D Related Documentation Note You can list all the available debugger commands by entering the Help HE command alone You can view the syntax for a particular command by ente...

Page 50: ...GEVDEL Global Environment Variable Delete GEVDUMP Global Environment Variable s Dump NVRAM Header Data GEVEDIT Global Environment Variable Edit GEVINIT Global Environment Variable Initialize NVRAM Header GEVSHOW Global Environment Variable Show GN Go to Next Instruction GO Go Execute User Program GT Go to Temporary Breakpoint HE Help on Command s IBM Indirect Block Move IDLE Idle Master MPU IOC I ...

Page 51: ...atic Network Bootstrap Operating System NAP Nap MPU NBH Network Bootstrap Operating System and Halt NBO Network Bootstrap Operating System NIOC Network I O Control NIOP Network I O Physical NIOT I O Teach for Configuring Network Controller NOBR Breakpoint Delete NOCM No Concurrent Mode NOMA Macro Delete NOMAL Disable Macro Expansion Listing NOPA Printer Detach NOPF Port Detach NORB No ROM Boot NOS...

Page 52: ...ded for testing and troubleshooting the MVME5100 PF Port Format PFLASH Program FLASH Memory PS Put RTC into Power Save Mode RB ROMboot Enable RD Register Display REMOTE Remote RESET Cold Warm Reset RL Read Loop RM Register Modify RS Register Set RUN MPU Execution Status SD Switch Directories SET Set Time and Date SROM SROM Examine Modify ST Self Test SYM Symbol Table Attach SYMS Symbol Table Displ...

Page 53: ...isted in Table 3 2 Note that not all tests are performed on the MVME5100 Using the HE command you can list the diagnostic routines available in each test group Refer to the PPCBug Diagnostics Manual listed in Appendix D Related Documentation for complete descriptions of the diagnostic routines and instructions on how to invoke them Table 3 2 Diagnostic Test Groups Test Group Description EPIC EPIC ...

Page 54: ...at are set up only in a particular restart mode Refer to the documentation on a particular diagnostic for the correct mode 3 Test Sets marked with an asterisk are not available on the MVME5100 unless an IPMC712 or IPMC761 is mounted The ISABRDGE test is only performed if an IPMC761 is mounted on the MVME5100 If the MVME5100 is operating in PMC mode IPMC761 is not mounted then the test suite is byp...

Page 55: ...arving the CPU of its memory Additional features of the MVME5100 include dual Ethernet ports dual serial ports and up to 17MB of Flash Features Summary The table below lists the general features for the MVME5100 Refer to Appendix A Specifications for additional product specifications and information Table 4 1 MVME5100 General Features Feature Specification Microprocessors and Bus Clock Frequency M...

Page 56: ...ch as the MVME2600 and MVME2700 It is important to note that MVME712 and MVME761 compatibility is accomplished with the addition of the corresponding IPMC712 or IPMC761 an optional add on PMC card The IPMC712 and IPMC761 provides rear I O support for one single ended ultra wide SCSI device one parallel port four serial ports two synchronous for 761 and one for 712 and two asynchronous synchronous ...

Page 57: ...cessor MPC7410 100 MHz MPC604 Processor Bus VME P1 PCI Expansion System Registers FLASH 1MB to 17MB Clock Generator VME Bridge Universe 2 Ethernet 1 10 100TX Buffers RTC NVRAM WD M48T37V TL16C550 UART 9pin Front Panel VME P2 RJ45 PMC FrontI O PMC Front I O SLot1 Slot2 2 64 bit PMC Slots L2 Cache 1M 2M Ethernet 2 10 100TX 10 100TX RJ45 10 100TX Hawk X bus RJ45 DEBUG planar 712 761 or PMC IPMC761 RE...

Page 58: ...e flash memory size is 16MB Note that only 32 bit writes are supported for this bank of flash memory Application Note For Am29DL322C or Am29DL323C 32Megabit 4M x 8 Bit 2M x 16 bit CMOS 3 0 Volt only Flash Memory The Write Protect function provides a hardware method of protecting certain boot sectors If the system asserts V IL low signal on the WP ACC pin the device disables the program and erase c...

Page 59: ...The SBC mode is accomplished by configuring the on board jumpers and attaching an IPMC712 or IPMC761 PMC in PMC slot 1 of the MVME5100 PMC mode is backwards compatible with the MVME2300 MVME2400 PMC mode is accomplished by simply configuring the on board jumpers Note Refer to Chapter 6 Pin Assignments for P2 Input Output Mode jumper settings Input Output Interfaces The following subsections descri...

Page 60: ... Hawk ASIC There are four 32 bit timers on the board that may be used for system timing or to generate periodic interrupts Interrupt Routing Legacy interrupt assignment for the PCI ISA Bridge is maintained to ensure software compatibility between the MVME5100 and the MVME2700 while in SBC mode This is accomplished by using the corresponding on board IPMC712 or IPMC761 connector to route the PCI IS...

Page 61: ...ower RAM500 module The RAM500 incorporates a Serial ROM for system memory Serial Presence Detect SPD data A maximum of two expansion modules are allowed one bottom and one top If only one module is used the RAM500 module with the top configuration is recommended Features The following table lists the features of the RAM500 memory expansion module Functional Description The following sections descr...

Page 62: ... size is dependent upon the SDRAM devices installed Refer to Table 5 2 for memory options The RAM500 memory expansion module is connected to the host board with a 140 pin AMP 0 6mm Free Height plug connector If the expansion module is designed to accommodate another RAM500 module the bottom expansion module will have two 140 pin AMP connectors installed one on the bottom side of the module and one...

Page 63: ...ost board has its SPD addressable at AA The second RAM500 attached to the host board has its SPD addressable at AC This dynamic address relocation of the RAM500 SPD shall be done using the bottom side connector signal A1_SPD and A0_SPD Bottom side MVME5100 MEZ Connector A BA WE_L RAS_L CAS_L Buffer LVTH162244 Top side MVME5100 MEZ Connector DQMB1 DQ CKD 1 Bank of 9 x8 SDRAMS CS_E_L DQ CKD DQMB0 CS...

Page 64: ...ating system shutdown Turn the AC or DC power off and remove the AC cord or DC power lines from the system Remove the chassis or system cover s as necessary for access to the CompactPCI boards 3 Carefully remove the MVME5100 from its VME card slot and lay it flat with connectors P1 and P2 facing you 4 Inspect the RAM500 module that is being installed on the MVME5100 host board bottom configuration...

Page 65: ...to mate with the MVME5100 host board P1 and one to mate with the top RAM500 module J1 The top RAM500 module has only one connector since it needs to mate only with the RAM500 module directly underneath it and because an added connector on a tandum RAM500 configuration would exceed the height limitations in some backplanes If only one RAM500 module is being used a top module single connector config...

Page 66: ...Q26 DQ27 36 37 DQ28 DQ29 38 39 DQ30 DQ31 40 41 GND GND 42 43 DQ32 DQ33 44 45 DQ34 DQ35 46 47 DQ36 DQ37 48 49 DQ38 DQ39 50 51 3 3V 3 3V 52 53 DQ40 DQ41 54 55 DQ42 DQ43 56 57 DQ44 DQ45 58 59 DQ46 DQ47 60 61 GND GND 62 63 DQ48 DQ49 64 65 DQ50 DQ51 66 67 DQ52 DQ53 68 69 3 3V 3 3V 70 71 DQ54 DQ55 72 73 DQ56 DQ57 74 75 DQ58 DQ59 76 77 DQ60 DQ61 78 79 GND GND 80 81 DQ62 DQ63 82 83 CKD00 CKD01 84 Table 5 ...

Page 67: ... sides of the plug assemblies 85 CKD02 CKD03 86 87 CKD04 CKD05 88 89 3 3V 3 3V 90 91 CKD06 CKD07 92 93 BA1 BA0 94 95 A12 A11 96 97 A10 A09 98 99 GND GND 100 101 A08 A07 102 103 A06 A05 104 105 A04 A03 106 107 A02 A01 108 109 3 3V 3 3V 110 111 A00 CS_C0_L 112 113 CS_E0_L GND 114 115 CS_C1_L CS_E1_L 116 117 WE_L RAS_L 118 119 GND GND 120 121 CAS_L 3 3V 122 123 3 3V DQMB0 124 125 DQMB1 SCL 126 127 SD...

Page 68: ...nk of SDRAM for a maximum of 512MB of memory The pin assignments for this connector are as follows Table 5 4 RAM500 Top Side Connector J1 Pin Assignments 1 GND GND 2 3 DQ00 DQ01 4 5 DQ02 DQ03 6 7 DQ04 DQ05 8 9 DQ06 DQ07 10 11 3 3V 3 3V 12 13 DQ08 DQ09 14 15 DQ10 DQ11 16 17 DQ12 DQ13 18 19 DQ14 DQ15 20 21 GND GND 22 23 DQ16 DQ17 24 25 DQ18 DQ19 26 27 DQ20 DQ21 28 29 DQ22 DQ23 30 31 3 3V 3 3V 32 33 ...

Page 69: ... 78 79 GND GND 80 81 DQ62 DQ63 82 83 CKD00 CKD01 84 85 CKD02 CKD03 86 87 CKD04 CKD05 88 89 3 3V 3 3V 90 91 CKD06 CKD07 92 93 BA1 BA0 94 95 A12 A11 96 97 A10 A09 98 99 GND GND 100 101 A08 A07 102 103 A06 A05 104 105 A04 A03 106 107 A02 A01 108 109 3 3V 3 3V 110 111 A00 CS_E0_L 112 113 GND 114 115 CS_E1_L 116 117 WE_L RAS_L 118 119 GND GND 120 121 CAS_L 3 3V 122 123 3 3V DQMB1 124 125 SCL 126 Table ...

Page 70: ...ithin the MVME5100 Single Board Computer Programmer s Reference Guide The register is accessed through the I2C interface of the Hawk ASIC on the host board MVME5100 The RAM500 SPD is software addressable by a unique address as follows The first RAM500 attached to the host board has has an SPD address of AA The second RAM500 attached to the top of the first RAM500 has an SPD address of AC 127 SDA 1...

Page 71: ...r and the appropriate setting s for proper board operation Jumper Description Connector Description J1 RISCWatch Header J3 IPMC761 Interface J2 PAL Programming Header J8 Memory Expansion J4 Ethernet Port 2 Configuration J25 PCI Expansion Interface J11 J14 PMC Interface Slot 1 J6 J20 Operation Mode Jumpers J21 J24 PMC Interface Slot 2 J7 Flash Memory Selection P1 P2 VMEbus Interface J10 J17 Etherne...

Page 72: ...ash Memory Selection at Boot Pins 1 2 for Soldered Bank A Socketed Bank B Pins 2 3 for Socketed Bank B J10 J17 Ethernet Port 2 Selection set in conjunction with jumper J4 For Front Panel Ethernet Port 2 Pins 1 3 and 2 4 on Both Jumpers Front Panel Ethernet Port 2 For P2 Ethernet Port 2 Pins 3 5 and 4 6 on Both Jumpers set for 712 761 J15 System Controller VME Pins 1 2 for No SCON Auto SCON Pins 2 ...

Page 73: ...ignments for this connector are as follows 19 3 3V DB15 20 21 DBP1 GND 22 23 GND LANINT2_L 24 25 PIB_INT 3 3V 26 27 3 3V PIB_PMCREQ 28 29 PIB_PMCGNT GND 30 31 GND 3 3V 32 33 5 0V 5 0V 34 35 GND GND 36 37 5 0V 5 0V 38 39 GND GND 40 Table 6 1 IPMC761 Connector Pin Assignments continued Table 6 2 Memory Expansion Connector Pin Assignments Pin Assignment Pin 1 GND GND 2 3 DQ00 DQ01 4 5 DQ02 DQ03 6 7 D...

Page 74: ...1 3 3V 3 3V 52 53 DQ40 DQ41 54 55 DQ42 DQ43 56 57 DQ44 DQ45 58 59 DQ46 DQ47 60 61 GND GND 62 63 DQ48 DQ49 64 65 DQ50 DQ51 66 67 DQ52 DQ53 68 69 3 3V 3 3V 70 71 DQ54 DQ55 72 73 DQ56 DQ57 74 75 DQ58 DQ59 76 77 DQ60 DQ61 78 79 GND GND 80 81 DQ62 DQ63 82 83 CKD00 CKD01 84 85 CKD02 CKD03 86 87 CKD04 CKD05 88 89 3 3V 3 3V 90 91 CKD06 CKD07 92 93 BA1 BA0 94 95 A12 A11 96 Table 6 2 Memory Expansion Connec...

Page 75: ...pansion Connector J25 Pin Assignments This connector is used to provide PCI PMC expansion capability The pin assignments for this connector are as follows 97 A10 A09 98 99 GND GND 100 101 A08 A07 102 103 A06 A05 104 105 A04 A03 106 107 A02 A01 108 109 3 3V 3 3V 110 111 A00 CS_C0_L 112 113 CS_E0_L GND 114 115 CS_C1_L CS_E1_L 116 117 WE_L RAS_L 118 119 GND GND 120 121 CAS_L 3 3V 122 123 3 3V DQMB0 1...

Page 76: ...n Assignment Pin 1 3 3V GND 3 3V 2 3 PCICLK PMCINTA 4 5 GND PMCINTB 6 7 PURST PMCINTC 8 9 HRESET PMCINTD 10 11 TDO TDI 12 13 TMS TCK 14 15 TRST PCIXP 16 17 PCIXGNT PCIXREQ 18 19 12V 12V 20 21 PERR SERR 22 23 LOCK SDONE 24 25 DEVSEL SBO 26 27 GND GND 28 29 TRDY IRDY 30 31 STOP FRAME 32 33 GND GND 34 35 ACK64 Reserved 36 37 REQ64 Reserved 38 ...

Page 77: ... C BE2 44 45 AD1 AD0 46 47 AD3 AD2 48 49 AD5 AD4 50 51 AD7 AD6 52 53 AD9 AD8 54 55 AD11 AD10 56 57 AD13 AD12 58 59 AD15 AD14 60 61 AD17 AD16 62 63 AD19 AD18 64 65 AD21 AD20 66 67 AD23 AD22 68 69 AD25 AD24 70 71 AD27 AD26 72 73 AD29 AD28 74 75 AD31 AD30 76 Table 6 3 PCI Expansion Connector Pin Assignments continued Pin Assignment Pin ...

Page 78: ...7 C BE6 82 83 AD33 AD32 84 85 AD35 AD34 86 87 AD37 AD36 88 89 AD39 AD38 90 91 AD41 AD40 92 93 AD43 AD42 94 95 AD45 AD44 96 97 AD47 AD46 98 99 AD49 AD48 100 101 AD51 AD50 102 103 AD53 AD52 104 105 AD55 AD54 106 107 AD57 AD56 108 109 AD59 AD58 110 111 AD61 AD60 112 113 AD63 AD62 114 Table 6 3 PCI Expansion Connector Pin Assignments continued Pin Assignment Pin Table 6 4 PMC Slot 1 Connector J11 Pin ...

Page 79: ...3 26 27 AD22 AD21 28 29 AD19 5V 30 31 5V Vio AD17 32 33 FRAME GND 34 35 GND IRDY 36 37 DEVSEL 5V 38 39 GND LOCK 40 41 SDONE SBO 42 43 PAR GND 44 45 5V Vio AD15 46 47 AD12 AD11 48 49 AD09 5V 50 51 GND C BE0 52 53 AD06 AD05 54 55 AD04 GND 56 57 5V Vio AD03 58 59 AD02 AD01 60 61 AD00 5V 62 63 GND REQ64 64 Table 6 4 PMC Slot 1 Connector J11 Pin Assignments continued Pin Assignment Pin ...

Page 80: ...RST Pull down to GND 14 15 3 3V Pull down to GND 16 17 Not Used GND 18 19 AD30 AD29 20 21 GND AD26 22 23 AD24 3 3V 24 25 IDSEL1 AD23 26 27 3 3V AD20 28 29 AD18 GND 30 31 AD16 C BE2 32 33 GND Not Used 34 35 TDRY 3 3V 36 37 GND STOP 38 39 PERR GND 40 41 3 3V SERR 42 43 C BE1 GND 44 45 AD14 AD13 46 47 GND AD10 48 49 AD08 3 3V 50 51 AD07 Not Used 52 53 3 3V Not Used 54 55 Not Used GND 56 57 Not Used N...

Page 81: ...D 14 15 GND AD60 16 17 AD59 AD58 18 19 AD57 GND 20 21 5V Vio AD56 22 23 AD55 AD54 24 25 AD53 GND 26 27 GND AD52 28 29 AD51 AD50 30 31 AD49 GND 32 33 GND AD48 34 35 AD47 AD46 36 37 AD45 GND 38 39 5V Vio AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 49 AD37 GND 50 51 GND AD36 52 53 AD35 AD34 54 55 AD33 GND 56 57 5V Vio AD32 58 59 Reserved Reserved 60 61 Reserved GND 62 63 GND...

Page 82: ...MC1_23 P2 C12 PMC1_24 P2 A12 24 25 PMC1_25 P2 C13 PMC1_26 P2 A13 26 27 PMC1_27 P2 C14 PMC1_28 P2 A14 28 29 PMC1_29 P2 C15 PMC1_30 P2 A15 30 31 PMC1_31 P2 C16 PMC1_32 P2 A16 32 33 PMC1_33 P2 C17 PMC1_34 P2 A17 34 35 PMC1_35 P2 C18 PMC1_36 P2 A18 36 37 PMC1_37 P2 C19 PMC1_38 P2 A19 38 39 PMC1_39 P2 C20 PMC1_40 P2 A20 40 41 PMC1_41 P2 C21 PMC1_42 P2 A21 42 43 PMC1_43 P2 C22 PMC1_44 P2 A22 44 45 PMC1_...

Page 83: ...11 GND Not Used 12 13 CLK GND 14 15 GND PMCGNT2 16 17 PMCREQ2 5V 18 19 5V Vio AD31 20 21 AD28 AD27 22 23 AD25 GND 24 25 GND C BE3 26 27 AD22 AD21 28 29 AD19 5V 30 31 5V Vio AD17 32 33 FRAME GND 34 35 GND IRDY 36 37 DEVSEL 5V 38 39 GND LOCK 40 41 SDONE SBO 42 43 PAR GND 44 45 5V Vio AD15 46 47 AD12 AD11 48 49 AD09 5V 50 51 GND C BE0 52 53 AD06 AD05 54 55 AD04 GND 56 57 5V Vio AD03 58 59 AD02 AD01 6...

Page 84: ...8 29 AD18 GND 30 31 AD16 C BE2 32 33 GND Not Used 34 35 TDRY 3 3V 36 37 GND STOP 38 39 PERR GND 40 41 3 3V SERR 42 43 C BE1 GND 44 45 AD14 AD13 46 47 GND AD10 48 49 AD08 3 3V 50 51 AD07 Not Used 52 53 3 3V Not Used 54 55 Not Used GND 56 57 Not Used Not Used 58 59 GND Not Used 60 61 ACK64 3 3V 62 63 GND Not Used 64 Pin Assignment Pin 1 Reserved GND 2 3 GND C BE7 4 5 C BE6 C BE5 6 7 C BE4 GND 8 9 5V...

Page 85: ... GND Reserved 64 Pin Assignment Pin 1 PMC2_1 P2 D1 PMC2_2 P2 Z1 2 3 PMC2_3 P2 D2 PMC2_4 P2 D3 4 5 PMC2_5 P2 Z3 PMC2_6 P2 D4 6 7 PMC2_7 P2 D5 PMC2_8 P2 Z5 8 9 PMC2_9 P2 D6 PMC2_10 P2 D7 10 11 PMC2_11 P2 Z7 PMC2_12 P2 D8 12 13 PMC2_13 P2 D9 PMC2_14 P2 Z9 14 15 PMC2_15 P2 D10 PMC2_16 P2 D11 16 17 PMC2_17 P2 Z11 PMC2_18 P2 D12 18 19 PMC2_19 P2 D13 PMC2_20 P2 Z13 20 21 PMC2_21 P2 D14 PMC2_22 P2 D15 22 ...

Page 86: ...2 Z31 46 47 Not Used Not Used 48 49 Not Used Not Used 50 51 Not Used Not Used 52 53 Not Used Not Used 54 55 Not Used Not Used 56 57 Not Used Not Used 58 59 Not Used Not Used 60 61 Not Used Not Used 62 63 Not Used Not Used 64 Pin Assignment Pin Pin Row Z Row A Row B Row C Row D 1 PMC2_2 J24 2 PMC1_2 J14 2 5V PMC1_1 J14 1 PMC2_1 J24 1 2 GND PMC1_4 J14 4 GND PMC1_3 J14 3 PMC2_3 J24 3 3 PMC2_5 J24 5 P...

Page 87: ...the IPMC712 are listed in the following two tables 15 PMC2_23 J24 23 PMC1_30 J14 30 VD17 PMC1_29 J14 29 PMC2_22 J24 22 16 GND PMC1_32 J14 32 VD18 PMC1_31 J14 31 PMC2_24 J24 24 17 PMC2_26 J24 26 PMC1_34 J14 34 VD19 PMC1_33 J14 33 PMC2_25 J24 25 18 GND PMC1_36 J14 36 VD20 PMC1_35 J14 35 PMC2_27 J24 27 19 PMC2_29 J24 29 PMC1_38 J14 38 VD21 PMC1_37 J14 37 PMC2_28 J24 28 20 GND PMC1_40 J14 40 VD22 PMC1...

Page 88: ... O I VD20 PRBSY PMC2_27 J24 27 19 PMC2_29 J24 29 AFD VD21 PRPE PMC2_28 J24 28 20 GND SLIN VD22 PRSEL PMC2_30 J24 30 21 PMC2_32 J24 32 TXD3 VD23 INIT PMC2_31 J24 31 22 GND RXD3 GND PRFLT PMC2_33 J24 33 23 PMC2_35 J24 35 RTXC3 VD24 TXD1_232 PMC2_34 J24 34 24 GND TRXC3 VD25 RXD1_232 PMC2_36 J24 36 25 PMC2_38 J24 38 TXD3 VD26 RTS1_232 PMC2_37 J24 37 26 GND RXD3 VD27 CTS1_232 PMC2_39 J24 39 27 PMC2_41 ...

Page 89: ...DB7 VA28 PRSTB PMC2_12 J24 12 9 DB12 DBP VA29 P DB0 PMC2_13 J24 13 10 GND ATN VA30 P DB1 PMC2_15 J24 15 11 DB13 BSY VA31 P DB2 PMC2_16 J24 16 12 GND ACK GND P DB3 PMC2_18 J24 18 13 DB14 RST 5V P DB4 PMC2_19 J24 19 14 GND MSG VD16 P DB5 PMC2_21 J24 21 15 DB15 SEL VD17 P DB6 PMC2_22 J24 22 16 GND D C VD18 P DB7 PMC2_24 J24 24 17 DBP1 REQ VD19 P ACK PMC2_25 J24 25 18 GND I O VD20 P BSY PMC2_27 J24 27...

Page 90: ...tom edge of the MVME5100 provides the interface to the serial debug ports The RJ45 connector is for COM1 and the 9 pin header is for COM2 The pin assignments for these connectors are as follows 2 TD 3 RD 4 AC Terminated 5 AC Terminated 6 RD 7 AC Terminated 8 AC Terminated Pin Assignment Pin Assignment 1 DCD 2 RTS 3 GNDC 4 TXD 5 RXD 6 GNDC 7 CTS 8 DTR Pin Assignment 1 DCD 2 DSR 3 RXD 4 RTS 5 TXD 6 ...

Page 91: ...ME5100 and each bus domain has its own view of the memory map The following sections describe the MVME5100 memory organization from the following three points of view The mapping of all resources as viewed by the MPU processor bus memory map The mapping of onboard resources as viewed by PCI local bus masters PCI bus memory map The mapping of onboard resources as viewed by VMEbus masters VMEbus mem...

Page 92: ...maps to ROM FLASH Bank B socketed 1MB Flash For an example of the CHRP memory map refer to the following table For detailed processor memory maps including suggested CHRP and PREP compatible memory maps refer to the MVME5100 Series Single Board Computer Programmer s Reference Guide Table 7 1 Default Processor Memory Map Processor Address Size Definition Start End 0000 0000 7FFF FFFF 2GB Not Mapped...

Page 93: ...this address maps to ROM FLASH Bank B Table 7 2 Suggested CHRP Memory Map Processor Address Size Definition Notes Start End 0000 0000 top_dram dram_size System Memory onboard DRAM 1 top_dram 8000 0000 variable PCI Memory Space 1 5 8100 0000 9FFF FFFF 512MB A32 D32 space mapped to VMEbus starting address of 0100 0000 A000 0000 A1FF FFFF 32MB A24 D16 space mapped to VMEbus starting address of F000 0...

Page 94: ...dge controller portion of the Hawk ASIC and by the Universe PCI VME bus bridge ASIC The Hawk and Universe devices adjust system mapping to suit a given application via programmable map decoder registers No default PCI memory map exists Resetting the system turns the PCI map decoders off and they must be reprogrammed in software for the intended application For detailed PCI memory maps including su...

Page 95: ...PU at a time have control of the MVME5100 control registers Of particular note are Registers that modify the address map Registers that require two cycles to access VMEbus interrupt request registers PCI Arbitration There are seven potential PCI bus masters on the MVME5100 Hawk ASIC MPU PCI bus bridge controller Winbond W83C554 PIB PCI ISA bus bridge controller DECchip 21143 Ethernet controller Un...

Page 96: ...PCI MEMORY SPACE PCI ISA MEMORY SPACE PCI I O SPACE MPC RESOURCES NOTE 1 NOTE 1 NOTE 2 NOTE 3 ONBOARD MEMORY 1 Programmable mapping done by Hawk ASIC 2 Programmable mapping performed via PCI Slave images in Universe ASIC 3 Programmable mapping performed via Special Slave image SLSI in Universe ASIC NOTES Table 7 4 PCI Arbitration Assignments PCI Bus Request PCI Master s PIB Internal PIB CPU Hawk A...

Page 97: ...SIC itself timer interrupts transfer error interrupts or memory error interrupts The processor processor self interrupts The PCI bus interrupts from PCI devices The ISA bus interrupts from ISA devices Figure 7 2 illustrates interrupt architecture on the MVME5100 For details on interrupt handling refer to the MVME5100 Series Single Board Computer Programmer s Reference Guide Figure 7 2 MVME5100 Int...

Page 98: ...tion controlled by the Port 92 register in the PIB resets the VMEbus when the MVME5100 is system controller 5 PCI ISA I O Reset function controlled by the Clock Divisor register in the PIB 6 The VMEbus SYSRESET signal 7 VMEbus Reset sources from the Universe ASIC PCI VME bus bridge controller the System Software reset Local Software Reset and VME CSR Reset functions Note On the MVME5100 Watchdog T...

Page 99: ...an by performing address rearrangement and reordering when running in little endian mode The MPC registers in the Hawk MPU PCI bus bridge controller SMC memory controller as well as DRAM Flash and system registers always appear as big endian Role of the Hawk ASIC Because the PCI bus is little endian the PHB portion of the Hawk performs byte swapping in both directions from PCI to memory and from t...

Page 100: ...niverse ASIC Because the PCI bus is little endian while the VMEbus is big endian the Universe PCI VME bus bridge ASIC performs byte swapping in both directions from PCI to VMEbus and from VMEbus to PCI to maintain address invariance regardless of the mode of operation in the processor s domain VMEbus Domain The VMEbus is inherently big endian All devices connected directly to the VMEbus must opera...

Page 101: ... those modules General Specifications The following table lists general specifications for MVME5100 Single Board Computer Table A 1 MVME5100 Specifications Characteristic Specification Operating Temperature 0 C to 55 C commercial and 20 C to 71 C industrial inlet air temperature with forced air cooling 400 LFM Linear Feet per Minute of forced air cooling is recommended for operation in the upper t...

Page 102: ...MC compliant chassis and meets the requirements for EN55022 Class B equipment Compliance was achieved under the following conditions Shielded cables on all external I O ports Cable shields connected to earth ground via metal shell connectors bonded to a conductive module front panel Conductive chassis rails connected to earth ground This provides the path for connecting shields to earth ground Fro...

Page 103: ...Condition Possible Problem Possible Resolution I Nothing works no display on the terminal A If the LEDs are not lit the board may not be getting power 1 Make sure the system is plugged in 2 Check that the board is securely installed in its backplane or chassis 3 Check that all necessary cables are connected to the board 4 Review the Installation and Startup procedures in this manual They include a...

Page 104: ... Disconnect all power from your system 2 Check that the proper debugger devices are installed 3 Reconnect power 4 Restart the system using the ABT RST switch press and hold switch down approximately 3 5 seconds 5 If the debug prompt appears go to step IV or step V as indicated If the debug prompt does not appear go to step VI B The board may need to be reset IV Debugprompt PPC6 Bug appears at powe...

Page 105: ...mand see your board Debugger Manual to change clock speed and or Ethernet Address and then later return to env CR and step 3 7 Run the selftests by typing in st CR The tests take as much as 10 minutes depending on RAM size They are complete when the prompt returns The onboard selftest is a valuable tool in isolating defects 8 The system may indicate that it has passed all the selftests Or it may i...

Page 106: ...ve cannot be corrected using the steps given A There may be some fault in the board hardware or the on board debugging and diagnostic firmware 1 Document the problem and return the board for service 2 Phone 1 800 222 5640 TROUBLESHOOTING PROCEDURE COMPLETE Table B 1 Troubleshooting Problems continued Condition Possible Problem Possible Resolution ...

Page 107: ...o conduct thermal evaluations of the board in their specific system configuration It identifies thermally significant components and lists the corresponding maximum allowable component operating temperatures It also provides example procedures for component level temperature measurements Thermally Significant Components Table C 1 summarizes components that show significant temperature rises You sh...

Page 108: ...bient U31 MPC952 125 Junction U32 MPC972 125 Junction U21 ECC DRAM NEC D4564841G5 70 Ambient U16 ECC DRAM NEC D4564841G5 70 Ambient U19 PPC7400 400 MHz Max 105 Junction U53 Pulse H0009 2 9942 C 85 Ambient 1 maximum temperature for reliable operation specified by the component manufacturer Table C 2 Thermally Significant Components on the IPMC761 Module Reference Designator Generic Description Maxi...

Page 109: ...ng in a maximum ambient temperature of 55 degrees C if the required airflow of 400 LFM is provided Customer findings my differ based on specific environmental and operational characteristics Figure C 1 Thermally Significant Components on the MVME5100 SBC Primary Side 2788 0406 P1 P2 J22 J24 J12 J14 J3 J5 J6 J21 J23 J11 J13 XU1 XU2 L2 L1 J8 J25 J10 J17 J7 J10 J15 J1 PCI MEZZANINE CARD 10 100 BASE T...

Page 110: ...measurement methods For the specific types of measurements required for thermal evaluation of this board see Table C 1 Preparation We recommend 40 gage thermocouples for all thermal measurements Larger gage thermocouples can wick heat away from the components and disturb air flowing past the board 2844 1100 P12 P14 P11 P13 DS2 DS1 U5 J3 U12 U6 C10 U11 J2 C8 C9 C7 C5 C2 C4 U3 IPMC761 SCSI BUSY PIB ...

Page 111: ...e the case temperature at the center of the top of the component Make sure there is good thermal contact between the thermocouple junction and the component We recommend you use a thermally conductive adhesive such as Loctite 384 If components are covered by mechanical parts such as heatsinks you need to machine these parts to route the thermocouple wire Make sure that the thermocouple junction co...

Page 112: ...s method is conservative since it includes heating of the air by the component Figure C 4 shows one method of mounting the thermocouple HEATSINK BOTTOM VIEW ISOMETRIC VIEW Machined groove for thermocouple wire routing Thermocouple junction bonded to component Heatsink base Thermal pad Through hole for thermocouple junction clearance may require removal of fin material Also use for alignment guidan...

Page 113: ...hermal Analysis MVME51005E Single Board Computer Installation and Use 6806800A38B 95 Figure C 4 Measuring Local Air Temperature Thermocouple junction PWB Tape thermocouple wire to top of component Air flow ...

Page 114: ......

Page 115: ...ervices Technical Documentation Search This site provides the most up to date copies of Emerson Network Power Embedded Computing product documentation Table D 1 Emerson Network Power Embedded Computing Publications Document Title Emerson Publication Number MVME5100 Single Board Computer Programmer s Reference Guide V5100A PG MVME7616E Transition Module Installation and Use 6806800A43 MVME712M6E Tr...

Page 116: ...eescale Product Information http www freescale com webapp sps library prod_lib jsp MPC750UM AD MPC7400UM D Universe II User Manual Tundra Semiconductor Corporation http www tundra com 9000000 MD303 01 Dallas Semiconductor DS1621 Digital Thermometer and Thermostat Dallas Semiconductor http www dalsemi com DS1621 LEVEL ONE LXT970 Fast Ethernet Transceiver Data Sheet http www amd com us en LXT970 Tex...

Page 117: ...note that while these sources have been verified the information is subject to change without notice Table D 3 Related Specifications Document Title and Source Publication Number Peripheral Component Interconnect PCI Interface Specification Revision 2 1 PCI Special Interest Group http www pcisig com PCI Local Bus Specification Common Mezzanine Card Specification PCI Mezzanine Card Specification IE...

Page 118: ......

Page 119: ...items MVME5100 base board 3 configurations MVME5100 xv configure PPC1Bug parameters 21 VMEbus interface 28 configuring the hardware 3 connector on RAM500 44 cooling requirements 84 D DEBUG port 12 debugger directory 35 prompt 18 debugger commands 31 DECchip 21143 LAN controller 77 diagnostics directory 35 hardware 34 prompt 18 test groups 35 dimensions MVME5100 83 directories debugger and diagnost...

Page 120: ...alization process as performed by firmware 19 Input Output Interface 41 installation RAM500 46 installation considerations 4 installing multiple MVME5100 boards 6 MVME5100 11 MVME5100 hardware 6 MVME5100 into chassis 11 PCI mezzanine cards 7 PMCs 7 PMCspan 8 9 primary PMCspan 8 secondary PMCspan 9 Internal Clock Frequency 37 interrupt from ABORT switch 13 interrupt architecture MVME5100 79 Interru...

Page 121: ...79 PCI Expansion Connector 38 PCI Expansion Interface 53 PCI expansion slot arbiter 77 PCI Host Bridge 37 PCI throughput 37 PCI PMC Expansion 38 Peripheral Support 38 PHB SMC of Hawk ASIC 73 PIB controller 77 pin assignments IPMC761 J3 54 pinouts J1 P1 RAM500 47 PMC slot 1 arbiter 77 slot 2 arbiter 77 PMC Carrier Board Placement on MVME5100 10 PMC Interface Slot 1 53 PMC Interface Slot 2 53 PMC mo...

Page 122: ...er 14 switch abort 13 reset 13 switches 13 switches MVME5100 front panel 13 SYSFAIL 23 system console connecting 12 system controller 11 System Controller VME 53 system controller function 13 System Memory Controller and PCI Host Bridge 40 system reset signal 13 T temperature operating 83 storage 83 terminal setup 12 testing the hardware 34 thermal analysis 89 thermally significant components 90 t...

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