3 PPCBug Firmware
MVME51005E Single Board Computer Installation and Use (6806800A38B)
27
Memory Size Ending Address = 02000000?
The default Ending Address is the calculated size of local memory. If the memory start is
changed from 0x0x00000000, this value will also need to be adjusted.
DRAM Speed in NANO Seconds = 15?
The default setting for this parameter will vary depending on the speed of the DRAM memory
parts installed on the board. The default is set to the slowest speed found on the available banks
of DRAM memory.
ROM Bank A Access Speed (ns) = 80?
This defines the minimum access speed for the Bank A Flash Device(s) in nanoseconds.
ROM Bank B Access Speed (ns) = 70?
This defines the minimum access speed for the Bank B Flash Device(s) in nanoseconds.
DRAM Parity Enable [On-Detection/Always/Never - O/A/N] = O?
Note
This parameter also applies to enabling ECC for DRAM.
L2 Cache Parity Enable [On-Detection/Always/Never - O/A/N] = O?
PCI Interrupts Route Control Registers (PIRQ0/1/2/3) = 0A0B0E0F?
Initializes the PIRQx (PCI Interrupts) route control registers in the IBC (PCI/ISA bus bridge
controller). The
ENV
parameter is a 32-bit value that is divided by 4 fields to specify the values
for route control registers PIRQ0/1/2/3. The default is determined by system type as shown:
PIRQ0=0A, PIRQ1=0B, PIRQ2=0E, PIRQ3=0F.
LED/Serial Startup Diagnostic Codes
These codes can be displayed at key points in the initialization of the hardware devices. The
codes are enabled by an
ENV
parameter.
Serial Startup Code Master Enable [Y/N]=N?
Should the debugger fail to come up to a prompt, the last code displayed will indicate how far
the initialization sequence had progressed before stalling.
Serial Startup Code LF Enable [Y/N]=N?
O
DRAM parity is enabled upon detection. (Default)
A
DRAM parity is always enabled.
N
DRAM parity is never enabled.
O
L2 Cache parity is enabled upon detection. (Default)
A
L2 Cache parity is always enabled.
N
L2 Cache parity is never enabled.
