Elan Digital Systems Ltd.
21
AD125 USER’S GUIDE
3.5.2 INPUT MUX CONTROL
There are 8 input channels to the AD12x and 16 to the AD13x. The
channels can be used either in single ended mode i.e. number of
input channels equals 8 (AD12x) or 16 (AD13x) OR they can be set
to work in true differential mode giving 4 channels (AD12x) or 8
channels (AD13x). Refer to the pinout table for details of which
channels are “differential pairs”.
The channels are multiplexed by fault protected muxes at the “front
end” of the card. The muxes are controlled by a 4-bit address
generated by an up counter. The MUXSEQ register controls the
counting “span” of the counter. The register is 8-bits wide and is
organised as 2 x 4-bit addresses. The mux counter is pre-loaded
with bits0..3 of the MUXSEQ register (start address) and counts up
to bits4..7 (end address). It then wraps back to the starting address
again. Before starting conversions the mux counter MUST be pre-
loaded with the start address from the MUXSEQ register by setting
the SELCTRD bit in SUR2 and then writing don’t care data to the
CLRCT port (remember... i) that this will undo any setup for pre-
trigger that you may have made so the order of events is important
ii) to set SELCTRD low again iii) that setting SELCTRD to a 1 will
clear any pending interrupt). After each conversion, the mux
counter is incremented by one. The MUXSEQ register does not
change during conversions; it is provides permanent storage of the
start and end addresses.
The bit significance of the 4 bit counter changes depending whether
the card is in single ended or differential mode. In single ended
mode all four bits are used to cycle through the input channels in the
order in which they are numbered i.e. A1, A2, A3 etc. In differential
mode, the MSB of the counter is not used. When loading the
MUXSEQ register and operating in differential mode be sure to set
both bit3 and bit7 to zero (i.e. the MSBs of the start and end
addresses). In differential mode the 3 bit count value is used to
cycle channels in pairs i.e. A1&A5, A2&A6, A3&A7 etc.
