Elan Digital Systems Ltd.
32
AD125 USER’S GUIDE
4.1 SETUP REG 2 (IR 1)
BIT
FUNCTION
RESET
STATE
WRITE
READ
0
IBITSEL0
See IBITSEL1.
IBITSEL0
0
1
IBITSEL1
MSBit of 2-bit interrupt select:
00: Interrupt when buffer full
01: Interrupt every
½
buffer full
10: Interrupt every
¼
buffer full
11: Interrupt every conversion
Only applies in FIFO mode.
IBITSEL1
0
2
BIPOLAR
Set high to use Bipolar input ranges,
set low for Unipolar
BIPOLAR
0
3
SINGLEEND
Set high to use Single Ended input
channels, set low for Differential
SINGLEEND
0
4
TREDGE
SET when set high in non-
level mode or > when set high in
level mode. Selects -ET when set
low in non-level mode or < when set
low in level mode.
TREDGE
0
5
LVL
Select level mode when set.
LVL
0
6
SELCTRD
Set low to read READ POINTER or
high to read WRITE POINTER.
Also used to clear IREQs when set
high. Set 0-1-0 to clear an IREQ.
Also used to pre-load the MUXSEQ
counter when high...see Input Mux
Control section for details.
SELCTRD
0
7
SINGLE
Set high when in FIFO mode to
allow nRUN to invoke a single
conversion. Set high in BURST
mode to “release” READ POINTER
after AD125 has halted to allow
SRAM to be read out.
SINGLE
0
