Elan Digital Systems Ltd.
29
AD125 USER’S GUIDE
4. AD125 REGISTER INTERFACE
The AD125 decodes the incoming PCMCIA interface. It maps the
CIS EPROM to 0-3FF,800-BFF etc. in attribute space. The range
400-7FF is occupied by the PCMCIA config option register inside
the AD125 (it repeats every byte). Both the CIS and COR are
always active.
The COR is used as a master enable, as defined by PCMCIA 2.01.
That is, when a valid config is written in bits0..5 the card's I/O
interface may function. Until this has happened, the card's I/O
interface is disabled. A config value of 0 will disable the card (NB
this is the state after a reset). Valid CONFIG values are 01
d
or 02
d
or
05
d
.
See the section on the COR for details of the various modes.
Bit7 of the COR acts as a soft reset when set (the reset does not
clear bit7 but a subsequent write to the config register to return bit 7
to zero should not attempt to load data into bits 6..0 of the register as
they will still clear. This should be done as a separate write
operation.)
All AD125 functions are accessed via three I/O ports (starting at
IOBASE as mapped by the host controller). The AD125 decodes A0
and A1, giving an Index Register (IR) at 0, a Data
Register (DR) at 1 and the SRAM data port at
2&3. The IR is 8-bits wide and is write only. The IR
selects which internal register is to be read/written via the DR (cf
82365 PCIC). The DR is also 8-bits wide. It is the job of the host
socket controller to map the IR, DR and SRAM data registers into
the system’s IO space starting at IOBASE and ending at 3.
