ELAN DIGITAL SYSTEMS LTD. AD121 User Manual Download Page 31 | Manualshive

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Elan Digital Systems Ltd.

31

AD125 USER’S GUIDE

4.0 SETUP REG 1 (IR 0)

BIT

FUNCTION

RESET
STATE

WRITE

READ

0

nRUN

Set low to start the AD125 taking

conversions or to start a SINGLE

conversion.

nRUN

1

1

nENTRIG

Set low to enable triggering i.e.

ARM the AD125 (BURST mode

only).

nENTRIG

1

2

nTIMING

Set low to enable a ¼ clock period

subtraction from the PACER

divider.

nTIMING

1

3

nSLEEP

Set low to put AD125 into low

power SLEEP mode.

nSLEEP

0

4

GS0

LSB of gain set code

GS0

0

5

GS1

GS1

0

6

GS2

GS2

0

7

GS3

MSB of gain set code

GS3

0

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Summary of Contents for AD121

Page 1: ...S AD135 AD126 AD136 AD132 AD121 AD131 AND MF2xx SERIES CARDS REVISION HISTORY ISSUE PAGES DATE NOTES 1 50 30 10 96 FIRST ISSUE 2 50 06 03 97 CORRECTION TO SAMPLE RATE CALCULATIONS 3 50 06 06 97 REDUCE...

Page 2: ...FORMAT GAIN SETTING 12 3 3 AD125 BUFFER ADDRESSING 14 3 3 1 BUFFER DATA ORDER 14 3 3 2 CONTROLLING THE SRAM POINTERS 14 3 3 3 PRE TRIGGER DEPTH 15 3 3 4 READING THE SRAM DATA 16 3 4 TRIGGERING 17 3 4...

Page 3: ...right to make changes without prior notice to any products herein to improve functionality reliability or other design aspects Elan does not assume any liability out of the use of any product describ...

Page 4: ...rigger threshold for BURST mode Programmable pre trigger depth This guide aims to familiarise you with the way that the AD125 works and so will help you to maximise its performance in your application...

Page 5: ...family of cards follows these naming conventions AD1 X Y for A to D cards MF2 X Y for Multi function A to D and D to A cards X 2 8 single ended channels 3 16 single ended channels Y 1 100KSPS max samp...

Page 6: ...t bit decision first as this is the most coarse level i e is the signal positive or negative Subsequent decisions are then made on the difference between the output of the internal D to A converter an...

Page 7: ...roperly designed digital filter This will depend on the exact application Bear in mind that this averaging could reduce the bandwidth of the data you are acquiring and will increase the settling time...

Page 8: ...ctory calibration constants is held on the card and can be accessed by software to compensate for this error is required 3 Avoid ground loops These can be caused when the source s ve side is connected...

Page 9: ...card s AGND level This will give you the maximum amount of headroom for the signal You can arrange this without making a direct connection using an external resistor of say 10K to pull the side close...

Page 10: ...t into RUN mode but with trigger disabled The AD125 starts taking samples After some elapsed time software sets ENTRIG to on to arm the system The AD125 will then wait until the incoming sample data m...

Page 11: ...bler C software 300KSPS should be possible but the speed depends heavily on what happens to the data once it is in the PC i e displayed written to disk etc The REP INSW PC Assembler codes are essentia...

Page 12: ...POLAR UNIPOLAR F S FULL SCALE BINARY HEX BINARY HEX F S 011111111111 7FF 111111111111 FFF F S 1LSB 011111111110 7FE 111111111110 FFE 0 2LSB 000000000010 002 000000000010 002 0 1LSB 000000000001 001 00...

Page 13: ...he following table summarises the gains and input ranges available GAIN GS0 3 AD125 INPUT VOLTAGE RANGE volts BIPOLAR UNIPOLAR 4 0h 0 625 0 1 25 2 1h 1 25 0 2 5 4 3 2h 1 875 0 3 75 1 3h 2 5 0 5 0 4 5...

Page 14: ...ddress bytes When cleared they are set to 7FFFh Each read by the PC of a byte of data decrements the READ POINTER by one Each conversion event decrements the WRITE POINTER by two 3 3 2 CONTROLLING THE...

Page 15: ...unters 3 If in FIFO mode pulse the SELCTRD bit in SETUP REG 2 to 0 1 0 to clear the possible artificial IREQ event caused by the internal counter outputs changing state The READ and WRITE POINTERS can...

Page 16: ...URST acquisition then the READ POINTER must be released temporarily to read out the A to D data This is achieved by setting SINGLE mode Bit 7 in SETUP REG 2 Be sure to return this bit to zero before a...

Page 17: ...Vfs full scale input voltage Unipolar mode TRIGBYTE ROUND 256 Vtrig Vfs Vfs full scale input voltage Remember that the value loaded into the trigger threshold register varies depending on the full sc...

Page 18: ...g TRIGGER WHEN I P TRANSITIONS FROM ABOVE Vtrig TO BELOW Vtrig TRIGGER WHENEVER I P IS ABOVE Vtrig TRIGGER WHENEVER I P IS BELOW Vtrig The modes are programmed via SETUP REG 2 The AD125 can also be tr...

Page 19: ...TRIGGER The AD125 will not trigger unless Bit 1 of SETUP REG 1 is low This allows software to arm the AD125 only when it is appropriate to do so i e after some start up condition or when the user has...

Page 20: ...it RESET DIVHI round 1 FSample 200E 9 1 75 8 DIVLO round 1 FSample 200E 9 1 75 255 so FSample 1 200E 9 DIVHI DIVLO 1 75 Where FSample is in Hz This gives FSample min 305 1Hz count 0x3FFF FSample max 2...

Page 21: ...MUST be pre loaded with the start address from the MUXSEQ register by setting the SELCTRD bit in SUR2 and then writing don t care data to the CLRCT port remember i that this will undo any setup for p...

Page 22: ...word This provides a useful way of keeping track of which samples came from which input channel The MUX address changes approximately 100ns after the track and hold enters hold mode for the current co...

Page 23: ...tive then back to inactive This allows internal clock generation to stabilise prior to taking any ADC readings Failure to do this can show as a bad first sample from the ADC directly after power up 3...

Page 24: ...it 4 0 INTERRUPT PENDING 1 NO INTERRUPT The interrupt from the AD125 is latched It must be cleared before another interrupt can be generated To clear it read from the SRAM buffer It can also be cleare...

Page 25: ...o enable a particular mode The COR is at 400h in attribute space and is 8 bits wide read write It is organised as follows BIT0 Config value LSB BIT1 BIT2 BIT3 BIT4 BIT5 Config value MSB BIT6 Not used...

Page 26: ...ION OF IOPIN2 BIT2 DIRECTION OF IOPIN3 4 BIT3 DIRECTION OF IOPIN5 6 7 8 Setting a bit high enables the pin group of pins as outputs The data to from the pins is read via the IODATA register as an 8 bi...

Page 27: ...it data 1 stop bit so move data opcode one place left code2 1 to make the stop bit For speed this routine compiles a list of byte wide Digital IO data and blats its in one go using a block write cmds...

Page 28: ...ing the interrupt configuration of the FIFO run mode of the card this interrupt can occur i every sample ii every quarter buffer i e every 4096 Fsample seconds iii every half buffer i e every 8192 Fsa...

Page 29: ...on the COR for details of the various modes Bit7 of the COR acts as a soft reset when set the reset does not clear bit7 but a subsequent write to the config register to return bit 7 to zero should not...

Page 30: ...UP REG 2 SETUP REG 2 2 IODATA IODATA 3 IODIR 4 BIT IODIR 6 BIT 4 DIVLO ADDRCTLO 5 DIVHI 6 BIT ADDRCTHI 6 MUXSEQ N U 7 TRIGTHRESH N U 8 N U SETUP REG 1 8 BIT 9 CTLEN SETUP REG 2 A N U IODATA B N U IODI...

Page 31: ...o start a SINGLE conversion nRUN 1 1 nENTRIG Set low to enable triggering i e ARM the AD125 BURST mode only nENTRIG 1 2 nTIMING Set low to enable a clock period subtraction from the PACER divider nTIM...

Page 32: ...nels set low for Differential SINGLEEND 0 4 TREDGE Selects ET when set high in non level mode or when set high in level mode Selects ET when set low in non level mode or when set low in level mode TRE...

Page 33: ...1 IOPIN1 Control IOPIN1 IOPIN1 Status of IOPIN1 0 2 IOPIN2 Control IOPIN2 IOPIN2 Status of IOPIN2 0 3 IOPIN3 Control IOPIN3 IOPIN3 Status of IOPIN3 0 4 IOPIN4 Control IOPIN4 IOPIN4 Status of IOPIN4 0...

Page 34: ...3DIR Set high to enable as OUTPUTS IOPIN2 3DIR 0 3 IOPIN4 5 6 7DIR Set high to enable as OUTPUTS On MF series the upper four IOs are always outputs and this bit changes function to become WFGEN which...

Page 35: ...W 8 BIT WORD OF 14 BIT CLOCK DIVIDER SEE ALSO THE TIMING BIT IN SETUP REG 1 LOW 8 BIT WORD OF 16 BIT READ OR WRITE POINTER 4 5 DIVHI ADDRCTHI IR 5 BIT FUNCTION RESET STATE WRITE READ 0 DIV8 ADDRCT8 1...

Page 36: ...start address MSB 0 4 MUXSEQ4 end address LSB 0 5 MUXSEQ5 0 6 MUXSEQ6 0 7 MUXSEQ7 end address MSB 0 8 BIT VALUE USED TO CONTROL INPUT MUX SEQUENCING 4 7 TRIGTHRESH IR 7 BIT FUNCTION RESET STATE WRITE...

Page 37: ...L ACTIVE LENGTH OF READ AND WRITE POINTERS ALSO USED TO FORCE A PARTIAL RESET OF BOTH READ AND WRITE POINTERS BIT MAPPED 0x7F SETS 15 BIT 0x3F 14 0x1F 13 0x0F 12 0x07 11 0x03 10 0x01 9 0x00 8 BIT MUST...

Page 38: ...POINTER BY TWO 4 11 CLRCT IR F BIT FUNCTION RESET STATE WRITE READ 0 X X 1 X X 2 X X 3 X X 4 X X 5 X X 6 X X 7 X X ANY READ OR WRITE ACCESS TO THIS PORT WILL SET THE READ WRITE POINTERS TO 0x7FFF AND...

Page 39: ...NTIAL MODE 13 A11 AD135 6 ONLY ANALOG CH 11 CH 7 IN DIFFERENTIAL MODE 14 A15 AD135 6 ONLY ANALOG CH 15 CH 7 IN DIFFERENTIAL MODE 15 A12 AD135 6 ONLY ANALOG CH 12 CH 8 IN DIFFERENTIAL MODE 16 A16 AD135...

Page 40: ...1 NOMINAL ACCURACY 55ppm oC DRIFT RESOLUTION 12 BITS 11 2 AT NYQUIST SAMPLE RATES FROM 305SPS TO 500KSPS AD125 AD135 OR 625KSPS AD126 AD136 OR 250KSP AD132 OR 100KSPS AD121 131 PROGRAMMABLE IN SINGLE...

Page 41: ...40dB DECADE FOR AD132 AND AD1x1 DACS TWO LOW SPEED 12 BIT DACS ON MF SERIES CARDS DAC RANGES EACH DAC OUTPUTS 0 2 5V AND 10V 10V ACCURACY 0 2 5V RANGE 0 5 10V 10V 0 9 DAC O P IMPEDANCE 10O TYP DAC SET...

Page 42: ...g to be LSB LSB when averaged over 1000 readings ii for Bipolar mode it is the voltage applied to the card that causes the ADC reading to be 0 LSB when averaged over 1000 readings Full scale point is...

Page 43: ...NUMBER OF INs OR OUTs TRIGGERING PROGRAMMABLE 8 BIT THRESHOLD EDGE ET ET ENABLE SOFTWARE CAN ARM SYSTEM DURING RUN PRE TRIGGER FROM 1 TO 16383 CONVERSIONS BURST MODE MUX SEQUENCING FLEXIBLE MUX ADDRES...

Page 44: ...ifies greatly the enumeration process and configuration management task for your application The driver is supplied on the diskette provided Please refer to PCCARDGO DOC for further information 6 2 C...

Page 45: ...e AD125 a connection between these two is made at a single star point to help reduce digital ground noise coupling into the analogue sections If you can keep the two returns separate in a similar fash...

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