Embedded Solutions Page 20
IP429_Encoder/Decoder
#define IP429II_OE0_DEV1_L
0x40
// read from Device 1 port 1 lower half
#define IP429II_OE0_DEV1_U
0x42
// read from Device 1 port 1 upper half
#define IP429II_OE1_DEV1_L
0x44
// read from Device 1 port 2 lower half
#define IP429II_OE1_DEV1_U
0x46
// read from Device 1 port 2 upper half
#define IP429II_LD1_DEV1
0x48
// write to Device 1 TX port lower half
#define IP429II_LD2_DEV1
0x4a
// write to Device 1 TX port upper half
#define IP429II_CNTL_DEV1
0x4c
// write to Device 1 control word
There are up to 4 “3282” devices installed per board. Each “3282” has two receivers
and 1 transmitter port. To support the control of the part several addresses are defined
per channel and replicated for each channel. Each channel is independent of the other
channels. Some settings within each “channel” [
device installed
] are binding on the
assets of the channel. For example the receive rate can be programmed high or low
per channel and affects both receivers within the channel.
IP429II_OE0_DEV1_L
IP429II_OE0_DEV1_U
IP429II_OE1_DEV1_L
IP429II_OE1_DEV1_U
These four addresses are for the reading of data from receiver 1 or 2 of channel 0. One
should access Lower then Upper. Both addresses actually activate the same control
signal to the 3282, but provide a different sense to the SEL line to tell the 3282 which 16
bit word to enable onto the bus at that time. When “U” is accessed the DRx flag is
reset.
“L” corresponds to the lower [D15..0] 16 bits of the 32 bit ARINC 429 data word.
“U” corresponds to the upper [D31..16] 16 bits of the 32 bit ARINC 429 data word.
IP429II_LD1_DEV1
IP429II_LD2_DEV1
The load addresses are for loading the upper and lower words for transmission. Word 1
should be loaded before word 2. Word 1 corresponds to the lower word of data
[D15..0], and word 2 corresponds to the upper word [D31..16]
