Dynamic Engineering IP-429-II User Manual Download Page 6 | Manualshive

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Embedded Solutions Page 6

Product Description

ARINC 429 is a versatile standardized bus interface.  ARINC 429 is robust featuring
Manchester encoding and enough voltage swing to provide excellent noise immunity
and reasonable throughput rates.  ARINC 429 is the interface of choice for critical
applications; for example aircraft instrumentation and control.  There are many devices

supporting the 429 bus - printers, instrumentation, sensors and more.

IP-429-II makes it easy to gain access to the ARINC 429 bus.  Just connect; program a
few registers and use like an IO device.  Reference software, schematics and
debugging aides are available in the Engineering Kit.

IP-429-II is an upgrade to the original IP-429 design.  Dynamic Engineering designed

the original IP-429  in 1998 and both manufactured and licensed the design.
GreenSpring Computers, and later SBS manufactured the board under their licensing
agreements.

The base version of the upgraded design uses the same address and bit maps.  The
design is enhanced with the Time Trigger / Time Stamp capability now being included
on all versions and moved into the IO space.  The IO connector has the same signal

definitions.  The revision 2 and later boards have FLASH memory instead of the PROM
and the JTAG signals available on the IO connector.

Please refer to the web page for updated versions with enhanced features.  The new
versions will have different IDPROM definitions to allow differentiation in your system.
Previously purchased IP-429-II rev B and later boards can be updated to make use of
the new features.

IP-429-II is capable of providing up to 8 Receive and 4 Transmit channels of ARINC 429
compatible IO in one IP position.  Each of the eight (8) receive channels has a 32 bit
Time Tag register associated with it.  The Time Tag generator operates with a 1 uS
resolution.  When each new message is received the Data Ready signal from the 429
decoder device is used to trigger the time stamp for that channel.

In addition to the ARINC 429 capability, a parallel IO port is provided to allow custom

formats and specialized status to be implemented.  The hardware is capable of other
formats including 571, 575, and 706 with software set-up changes.

IP-429 supports both the High and Low speed standards for data transmission.  A
programmable register allows each TX channel to operate at either rate.  Each
transmitter is supported by an 8 deep 32 bit wide FIFO.

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Summary of Contents for IP-429-II

Page 1: ...ois St Suite C Santa Cruz CA 95060 831 457 8891 Fax 831 457 4793 Web Page http www dyneng com E Mail sales dyneng com Est 1988 User Manual IP 429 II ARINC 429 Interface IP Module Revision A1 Corresponding Hardware 10 2007 0501 2 ...

Page 2: ... liability arising out of the application or use of the device described herein The electronic equipment described herein generates uses and can radiate radio frequency energy Operation of this equipment in a residential area is likely to cause radio interference in which case the user at his own expense will be required to take whatever measures may be required to correct the interference Dynamic...

Page 3: ...REG1 14 IP429II_BASE_REG2 15 IP429II_BASE_REG3 15 IP429II_VECTOR 16 IP429II_STATUS0 17 IP429II_STATUS1 18 IP429II_Parallel 19 IP429_Encoder Decoder 20 IP429_CHx_CNTL 21 IP429_CHXX_TS 23 Interrupts 24 ID PROM 25 LOOP BACK 26 IP MODULE LOGIC INTERFACE PIN ASSIGNMENT 27 IP MODULE IO INTERFACE PIN ASSIGNMENT 28 APPLICATIONS GUIDE 29 Interfacing 29 Construction and Reliability 30 ...

Page 4: ...Embedded Solutions Page 4 Thermal Considerations 31 WARRANTY AND REPAIR 31 Service Policy 31 Out of Warranty Repairs 31 For Service Contact 32 SPECIFICATIONS 33 ORDER INFORMATION 34 ...

Page 5: ...URE 4 IP 429 CONTROL REGISTER 2 BIT MAP 15 FIGURE 5 IP 429 CONTROL REGISTER 3 BIT MAP 15 FIGURE 6 IP 429 STATUS REGISTER 0 BIT MAP 17 FIGURE 7 IP 429 STATUS REGISTER 1 BIT MAP 18 FIGURE 8 IP 429 CONTROL REGISTER 0 BIT MAP 19 FIGURE 9 IP 429 3282 CONTROL REGISTER BIT MAP 21 FIGURE 10 IP 429 ID PROM STANDARD 25 FIGURE 11 IP 429 LOGIC INTERFACE 27 FIGURE 12 IP 429 IO INTERFACE 28 ...

Page 6: ...o the IO space The IO connector has the same signal definitions The revision 2 and later boards have FLASH memory instead of the PROM and the JTAG signals available on the IO connector Please refer to the web page for updated versions with enhanced features The new versions will have different IDPROM definitions to allow differentiation in your system Previously purchased IP 429 II rev B and later...

Page 7: ...factors while maintaining plug and software compatibility system prototyping may be done on one IP Carrier board with final system implementation on a different one Dynamic Engineering carrier boards have Drivers available for Windows and Linux IP 429 II is supported with a Windows driver included with the purchase of the card This manual contains enough data to write your own driver should you pr...

Page 8: ...it states for read or write cycles to any address Hold cycles are supported as required by the host processor Data remains enabled during a read until the host removes the SEL line Local timing terminates a write cycle prior to SEL being de asserted The interface to the 429 encoder decoder modules is operated at 100 MHz to allow for precise timing with as little wasted time as possible The IO spac...

Page 9: ...iorities for responding to the interrupt s The interface can be operated in a polled mode by reading the status register If the system needs to know when data was received Time Tagging can be useful IP 429 II supports Time Tagging by providing a 32 bit counter which operates at 1 MHz to provide a 1 uS Time Tag count When the interrupt from any of the receive channels is asserted the current time i...

Page 10: ...Time Tag Device 2 receiver 2 D31 D16 read only define IP429II_TS_DEV3_CH1_LWR 0x24 Time Tag Device 3 receiver 1 D15 D0 read only define IP429II_TS_DEV3_CH1_UPR 0x26 Time Tag Device 3 receiver 1 D31 D16 read only define IP429II_TS_DEV3_CH2_LWR 0x28 Time Tag Device 3 receiver 2 D15 D0 read only define IP429II_TS_DEV3_CH2_UPR 0x2A Time Tag Device 3 receiver 2 D31 D16 read only define IP429II_TS_DEV4_...

Page 11: ...per half define IP429II_CNTL_DEV4 0x7c write to Device 4 control word FIGURE 1 IP 429 INTERNAL ADDRESS MAP The address map provided is for the local decoding performed within the IP 429 The addresses are all offsets from a base address The carrier board where the IP is installed provides the base address and controls the naming of the bytes We refer to the bytes following Motorola conventions i e ...

Page 12: ...erence for the IO state machine No programming required for this functionality Dynamic Engineering carriers come with Windows and other drivers The drivers are structured to detect the carrier and the installed IP modules The carrier driver will automatically load the appropriate IP module driver if available and the generic driver for that IP position if the installed IP is not in the list of sup...

Page 13: ...or software commonality but has no effect on operation INT_SET is used to force an interrupt condition to occur This control bit is useful for SW development and HW testing Default to no interrupt 0 force interrupt with 1 CLR_CNT is used to reset the 32 bit Time Stamp counter The clear bit is written with a 1 and then released with a 0 to set the counter to a 0 value and restore operation Please r...

Page 14: ...s bit is normally left programmed to 0 There is another control bit within the 3282 that also controls Parity along with even or odd sense It is recommended to use the 3282 control bit Default is 0 RESETx is used to reset the 3282 associated with each channel The channel should be reset when the 3282 control register is written to write only port Default is reset 0 1 normal operation Reset should ...

Page 15: ...ing needs to match the CNTL2 selections for speed This is a legacy register retained for software commonality but has no effect on operation The new transmitter does not require this input IP429II_BASE_REG3 06 429 Control Register Port read write CONTROL REGISTER 3 DATA BIT DESCRIPTION 7 Tx Int En 4 0 disabled 1 enabled 6 Tx Int En 3 0 disabled 1 enabled 5 Tx Int En 2 0 disabled 1 enabled 4 Tx Int...

Page 16: ...terrupt mask The individual receiver within each device is identifiable with STATUS0 Devices not populated on the board should be masked off 1 enabled and 0 disabled for the interrupt Default 0 The level from the DRx status lines from the 3282 are used to generate the interrupt After a reception the receive register has data available is causing the DRx line to transition low The line will remain ...

Page 17: ...der devices The signals are buffered and inverted to create active high data ready signals DR1 is receiver 1 of device N DR2 is receiver 2 of device N Each of the 4 channels has 2 receivers There are four devices and your hardware may not have all four installed Uninstalled devices should be masked off when reading this status register These bits can be used for polled operation of the receivers T...

Page 18: ... Transmitter Ready bits driven from the 3282 When high the bits indicate that the transmitter is ready to receive data The rising edge of the signal is used to create the TX completed interrupt as that edge indicates that the transmitter is ready to receive more data When the signal is low it indicates that the transmitter is ready to send If the SENDx bit is enabled then the transmission will beg...

Page 19: ...pen drain high sink drivers The read back comes from the bus side of the drivers If high then a low on the driver indicates another device is driving the line low The lines are pulled up with 1K pull up resistors and are terminated with 33Ω series resistors The upper 4 bits are read only and are terminated with 33Ω series terminators The port is configured with an 8 bit register The lower 4 bits a...

Page 20: ...channel device installed are binding on the assets of the channel For example the receive rate can be programmed high or low per channel and affects both receivers within the channel IP429II_OE0_DEV1_L IP429II_OE0_DEV1_U IP429II_OE1_DEV1_L IP429II_OE1_DEV1_U These four addresses are for the reading of data from receiver 1 or 2 of channel 0 One should access Lower then Upper Both addresses actually...

Page 21: ... Logic 0 enables self test and 1 places the device in normal mode In self test the data is transmitted to the receiver channels Receiver 1 receives the normal data and receiver 2 receives the complement When in self test mode some confusion can arise from the treatment of the parity bit The 3282 allows you to turn off parity on the transmitter but parity is always enabled for the receiver The rece...

Page 22: ...1 causes even parity and a 0 selects odd parity for the transmitter if PAREN is set TXSEL RCVSEL 0 100K transmit or receive speed and 1 selects 12 5K Transmitter needs to match the receiver of the data stream not necessarily the receiver within the same device Both receiver channels are affected by the selection within the same channel WLSEL Word length select 0 32 bits 1 25 bits in length In gene...

Page 23: ...o read both the L and U as a packed 32 bit word The base counter is 32 bits wide and counts up at a rate of 1 MHz When the Receive interrupt for a particular channel is detected the current count is stored into the Time Tag register for that channel The interrupt event used is electronically prior to the mask and operates even if the interrupt for a particular channel is masked off The Time Tag ca...

Page 24: ...request when a transmission or reception is complete and the INTEN bits in the control registers are set The interrupt is mapped to interrupt request 0 The CPU will respond by asserting INT The hardware will automatically supply the appropriate interrupt vector and clear the request when accessed by the CPU The source of the interrupt is obtained by reading the status registers The status remains ...

Page 25: ...e IP s I O space or at IP base 80 Dynamic Engineering parent drivers use the ID PROM automatically to instantiate the correct child driver for a particular slot Standard data in the ID PROM on the IP 429 II is shown in the figure below For more information on IP ID PROM s refer to the IP Module Logic Interface Specification available from Dynamic Engineering Each of the four dash versions of the I...

Page 26: ...e connections used for the Dynamic Engineering test software There are 4 possible devices and all are shown The first set is for Device 1 The first entry is for the A signal and the second for the B The second table is for the Parallel Port The lower signals are tied to the upper TX CH1 CH2 7 1 4 8 2 5 16 10 13 17 11 14 26 19 22 27 20 23 35 29 32 36 30 33 PIO 41 45 42 46 43 47 44 48 ...

Page 27: ...1 36 D8 A1 12 37 D9 n c 13 38 D10 A2 14 39 D11 n c 15 40 D12 A3 16 41 D13 IntReq0 17 42 D14 A4 18 43 D15 n c 19 44 BS0 A5 20 45 BS1 n c 21 46 12V A6 22 47 12V Ack 23 48 5V n c 24 49 GND GND 25 50 NOTE 1 The no connect signals above are defined by the IP Module Logic Interface Specification but not used by this IP See the Specification for more information NOTE 2 The layout of the pin numbers in th...

Page 28: ..._7 23 48 GND Fused 3 3V 24 49 GND GND 25 50 NOTE 1 The layout of the pin numbers in this table corresponds to the physical placement of pins on the IP connector Thus this table may be used to easily locate the physical pin corresponding to a desired signal Pin 1 is marked with a square pad on the IP Module FIGURE 12 IP 429 IO INTERFACE Please note the IO assignments reference all of the possible T...

Page 29: ...nents You provide the system Safety and reliability can be achieved only by careful planning and practice Inputs can be damaged by static discharge and by applying voltages exceeding the device specifications Terminal Block We offer a high quality 50 screw terminal block that directly connects to the flat cable The terminal block mounts on standard DIN rails http www dyneng com HDRterm50 html Carr...

Page 30: ...ed and shrouded with Gold plated pins on both plugs and receptacles They are rated at 1 Amp per pin 200 insertion cycles minimum These connectors make consistent correct insertion easy and reliable The IP is secured against the carrier with four metric M2 stainless steel screws The heads of the screws are countersunk into the IP The four screws provide significant protection against shock vibratio...

Page 31: ...unit in the original shipping carton if this is available and ship prepaid and insured with the RMA number clearly written on the outside of the package Include a return address and the telephone number of a technical contact For out of warranty repairs a purchase order for repair charges must accompany the return Dynamic Engineering will not be responsible for damages due to improper packaging of...

Page 32: ...Embedded Solutions Page 32 For Service Contact Customer Service Department Dynamic Engineering 150 DuBois St Suite C Santa Cruz CA 95060 831 457 8891 831 457 4793 fax Internet Address support dyneng com ...

Page 33: ...ARINC 429 data interface has longer access times required Wait States variable depending on clock rate and what is being accessed 1 7 Interrupt programmable DMA No Logic Interface DMA Support implemented at this time Onboard Options All Options are Software Programmable Interface Options 50 pin flat cable 50 screw terminal block interface User cable Dimensions Standard Single IP Module 1 8 x 3 9 x...

Page 34: ...temperature testing after conformal coating ROHS Standard solder processing is used unless ROHS is requested CableGnd After programming remove and add components to change JTAG and 3 3 to original GND definitions Not recommended for new designs provided for backward compatibility Tools for IP 429 x IP Debug Bus IP Bus interface extender http www dyneng com ipdbgbus html IP Debug IO IO connector br...

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