Embedded Solutions Page 21
IP429_CHx_CNTL
CONTROL REGISTER 0
DATA BIT
DESCRIPTION
15
WLSEL
14
RCVSEL
13
TXSEL
12
PARCK
11
Y2
10
X2
9
SDEN2
8
Y1
7
X1
6
SDEN1
5
/SLFTST
4
PAREN
3
UNUSED
2
UNUSED
1
UNUSED
0
UNUSED
FIGURE 9
IP-429 3282 CONTROL REGISTER BIT MAP
The details of programming the 3282 can be found in the DDC-ILC DATA Device
Corporation Data Book. A copy of the 3282 data sheet is available on our web site. The
file is available on the IP-429 page.
http://www.dyneng.com/ip429.html
A summary of the control bits follows.
PAREN - Transmitter Parity Enable. 0 = data 1 = parity if DBCEN is set low. If DBCEN
is programmed high then parity is always inserted independent of PAREN.
/SLFTST - Self Test Enable. Logic 0 enables self-test and 1 places the device in
normal mode. In self test, the data is transmitted to the receiver channels. Receiver 1
receives the normal data and receiver 2 receives the complement.
When in self test mode some confusion can arise from the treatment of the parity bit.
The '3282 allows you to turn off parity on the transmitter, but parity is always enabled for
the receiver. The receiver will calculate parity based on the entire 32-bit word. The
receiver will insert a logic zero for odd parity (no error) and a logic one for even parity
(error). In the case of writing 0x4321 and 0x8765, parity is odd so the receiver inserts a
logic zero into bit 8 of word 1. This explains why it is received as 0x4221. If you were
to write 0x5321 and 0x8765, you would receive 0x5321 and 0x8765. This would be an
error condition because parity is even and thus, bit 8 of word 1 is asserted
high. This is
