Embedded Solutions Page 8
Theory of Operation
IP-429-II is designed for the purpose of transferring data from one point to another with
the ARINC-429 protocol.
IP-429-II features a Xilinx FPGA and industry standard 3282 compatible ARINC 429
receiver / transmitter devices. The FPGA contains the IP interface and control required
for the 429 devices. Each 3282 provides two Receiver channels and one partial
Transmit channel. A separate device provides the “drive” circuitry for the transmit
channel. The ‘3282 data sheet is available on-line from the IP-429 webpage.
IP-429-II is a part of the IP Module family of I/O products. It meets the IP Module VITA
Standard. Contact VITA for a copy of this specification. It is assumed that the reader is
at least casually familiar with this document and logic design. In standard configuration
it is a Type II mechanical with passive low profile components on the back of the board
and one slot wide.
The bus interface to the host CPU is controlled by a logic block within the Xilinx device
that contains the decoding and timing elements required to interface to the IP bus
interface. The timing is referenced to the 8 or 32 MHz IP logic clock. The IP responds to
the ID, INT, MEM and IO selects. The FPGA design requires wait states for read or
write cycles to any address. Hold cycles are supported as required by the host
processor. Data remains enabled during a read until the host removes the SEL line.
Local timing terminates a write cycle prior to SEL being de-asserted.
The interface to the 429 encoder/decoder modules is operated at 100 MHz. to allow for
precise timing with as little wasted time as possible. The IO space decodes for the write
and read functions are set based on the IP clock rate. The state-machine detects the
request and handles the data transfer to/from the encoder/decoder. The number of
wait-states will depend on the IP clock rate in use. At 8 Mhz the timing of the
encoder/decoder is similar which will lead to fewer wait states. At 32 Mhz the IP clock is
faster than the read or write timing to the encoder/decoder leading to more wait-states.
The overall time will be shorter with the 32 MHz clock. If available it [32 MHz] is
recommended for use.
Before transmitting or receiving data IP-429-II requires register programming to select
data rates and formats as well as system clock speed, interrupt masking etc.. Each of
the programmable registers is described in the programming section. Once IP-429-II
has been set-up for operation in your environment, data can be transferred.
To transmit, data is loaded into the transmitter FIFO within the channel of interest and
the transmission enabled. If programmed, an interrupt will alert the host that the data
