Denon DN-V1700, Service Manual

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20
DN-V1700
127 Receive Data Valid RX_DV
I with Input from MII PHY. Envelope of data valid reception. Used for receive data
pulldown framing.
44 Local Bus Clock LCLK I**
Input. Used to interface synchronous buses. Maximum frequency is 50 MHz.
Limited to 8.33 MHz for EISA DMA burst mode.
Open drain output. ARDY may be used when interfacing asynchronous buses to
extend accesses. Its rising (access completion) edge is controlled by the XTAL1
40
Asynchronous
ARDY OD16
clock and, therefore, asynchronous to the host CPU or bus clock. ARDY is
Ready negated during Asynchronous cycle when one of the following conditions
occurs: 1) No_Wait Bit in the Configuration Register is cleared. 2) Read FIFO
contains less than 4 bytes when read. 3) Write FIFO is full when write.
nSynchronous
Output. This output is used when interfacing synchronous buses and nVLBUS=0
45
Ready
nSRDY O16 to extend accesses. This signal remains normally inactive, and its falling edge
indicates completion. This siganal is synchronous to the bus clock LCLK.
Input. This input is used to complete synchronous read cycles. In EISA burst
48 nReady Return nRDYRTN I** mode it is sampled on falling LCLK edges, and synchronous cycles are delayed
until it is sampled high.
Interrupt Output-Used to interrupt the Host on a status event.
31 Interrupt INTR0 O24
Note: The selection bits used to determined by the value of INT SEL 1-0 bits in
the Configuration Register are no longer required and have been set to
reserved in this revision of the FEAST family of devices.
Output. This active low output is asserted when AEN is low and A4-A15 decode
47 nLocal Device nLDEV O16
to the LAN91C111 address programmed into the high byte of the Base Address
Register. nLDEV is a combinatorial decode of unlatched address and AEN
signals.
33 nReady Strobe nRD IS** Input. Used in asynchronous bus interfaces.
34 nWrite Strobe nWR IS** Input. Used in asynchronous bus interfaces.
Input. When nDATACS is low, the Data Path can be accessed regardless of the
36
nData Path
nDATACS
I with values of AEN, A1-A15 and the content of the BANK SELECT Register.
Chip Select pullup** nDATACS provides an interface for bursting to and from the LAN91C111 32 bits
at a time.
83-94 Address A4-A15 I** Input. Decoded by LAN91C111 to determine access to its registers.
80-82 Address A1-A3 I** Input. Used by LAN91C111 for internal register selection.
43 Address Enable AEN I**
Input. Used as an address qualifier. Address decoding is only enabled when
AEN is low.
nBE0-
Input. Used during LAN91C111 register accesses to determine the width of the
96-99 nByte Enable
nBE3
I** access and the register(s) being access. nBE0-nBE3 are ignored when
nDATACS is low (burst accesses) because 32 bit transfers are assumed.
106-109,
101-104,
Bidirectional. 32 bit data bus used to access the LAN91C111’s internal registers.
75-78, 70-73, Data Bus D0-D31 I/O24** Data bus has weak internal pullups. Supports direct connection to the system
65-68, 60-63, bus without external buffering. For 16 bit systems, only D0-D15 are used.
55-58, 50-53
Input. When this pin is asserted high, the controller performs an internal system
(MAC&PHY) reset. It programs all the registers to their default value, the
32 Reset RESET IS** controller will read the EEPROM device through the EEPROM interface(1). This
input is not considered active unless it is active for at least 100ns to filter narrow
glitches.
Input. For systems that require address latching, the rising edge of nADS
39 nAddress Strobe nADS IS** indicates the latching moment for A1-A15 and AEN. All LAN91C111 internal
functions of A1-A15, AEN are latched except for nLDEV decoding.
37 nCycle nCYCLE I**
Input. This active low signal is used to control LAN91C111 EISA burst mode
synchronous bus cycle.
38 Write/nRead W/nR IS**
Input. Defines the direction of synchronous cycles. Write cycles when high, read
cycles when low.
I with
Input. When low the LAN91C111 synchronous bus interface is configured for VL
42 nVL Bus Access nVLBUS
pullup**
Bus accesses. Otherwise, the LAN91C111 is configured for EISA DMA burst
accesses. Does not affect the asynchronous bus interface.
114
Collision Detect
COL100
I with
Input from MII PHY. Collision detection input.
100 Mbps pulldown
115-118 Transmit Data
TXD0-
O12 Output. Transmit Data nibble to MII PHY.
TXD3
111 Transmit Clock TX25
I with Input. Transmit clock input from MII. Nibble rate clock
pullup (25MHz for 100Mbps & 2.5MHz for 10Mbps).
Description Pin No. Name
Buffer
Type
Symbol