Denon DN-V1700, Service Manual

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15
DN-V1700
Pin Name Pin No. Function I/O
138 D60 I/O Data
139 D50 I/O Data/Port (Port) (Port) (Port) (Port) (Port)
140 D61 I/O Data ACCSIZE0
141 D49 I/O Data/Port (Port) (Port) (Port) (Port) (Port)
142 D62 I/O Data ACCSIZE1
143 VDD Power Internal VDD (1.8V)
144 VSS Power Internal GND (0V)
145 D48 I/O Data/Port (Port) (Port) (Port) (Port) (Port)
146 D63 I/O Data ACCSIZE2
147 VDDQ Power IO VDD (3.3V)
148 VSSQ Power IO GND (0V)
149 MD0/SCK I/O Mode/SCI clock MD0 SCK SCK SCK SCK SCK
150 MD1/TXD2 I/O Mode/SCIF data output MD1 TXD2 TXD2 TXD2 TXD2 TXD2
151 MD2/RXD2 I Mode/SCIF data input MD2 RXD2 RXD2 RXD2 RXD2 RXD2
152 IRL0 I Interrupt 0
153 IRL1 I Interrupt 1
154 IRL2 I Interrupt 2
155 IRL3 I Interrupt 3
156 NMI I Non-maskable interrupt
157 XTAL2 O RTC crystal oscillator pin
158 EXTAL2 I RTC crystal oscillator pin
159 VSS-RTC Power RTC GND (0V)
160 VDD-RTC Power RTC VDD (3.3V)
Hardware standby request
161 CA I (SH7750S only), pull-up to
3.3V for SH7550
162 VSS Power Internal GND (0V)
163 VDDQ Power IO VDD (3.3V)
164 CTS2 I/O SCIF data control (CTS)
165 TCLK I/O RTC/TMU Clock
166 MD8/RTS2 I/O Mode/SCIF data control (RTS) MD8 RTS2 RTS2 RTS2 RTS2 RTS2
167 MD7/TXD I/O Mode/SCI data output MD7 TXD TXD TXD TXD TXD
168 SCK2/MRESET I/O SCIF clock/Manual reset MRESET SCK2 SCK2 SCK2 SCK2 SCK2
169 VDD Power Internal VDD (1.8V)
170 VSS Power Internal GND (0V)
171 A18 O Address
172 A19 O Address
173 A20 O Address
174 A21 O Address
175 A22 O Address
176 A23 O Address
177 VDDQ Power IO VDD (3.3V)
178 VSSQ Power IO GND (0V)
179 A24 O Address
180 A25 O Address
181 MD3/CE2A I/O Mode/PCMCIA-CE MD3 CE2A
182 MD4/CE2B I/O Mode/PCMCIA-CE MD4 CE2B
183 MD5/RAS2 I/O Mode/RAS (DRAM) MD5 RAS2
184 DACK0 O DMAC0 Bus recognition
185 DACK1 O DMAC1 Bus recognition
186 A0 O Address
187 VDDQ Power IO VDD (3.3V)
188 VSSQ Power IO GND (0V)
189 A1 O Address
190 STATUS0 O Status
191 STATUS1 O Status
192 MD6/IOIS16 I Mode/IOIS16 (PCMCIA) MD6 IOIS16
Memory Interface
Reset
SRAM DRAM SDRAM PCMCIA MPX