Denon DN-V1700, Service Manual

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18
DN-V1700
Pin Description Pin Name
I/O
During
Config.
I/O
After
Config.
FS ADJUST
VBIAS
VREF
VAA
COMP
AGND
AGND
CVBS/B
AGND
CVBS/G
AGND
C/R
A
GND
HSYNC VSYNC BLANK RESET VDD GND VDD3V CLK SLA
VE
SCL SD
A
SLEEP
TTXREQ
VDD
GND
P[7]
P[6]
P[5]
P[4]
P[3]
P[2]
P[1]
P[0]
TTXDAT
RGBOUT
FIELD
Y[0] Y[1]
GND
VDD
A
GND
Y/CVBS
Y[2] Y[6] Y[7] Y[5]
AL
T
ADDR
Y[3] Y[4]
14 15 16 17 18 19 20 21 22 23 24 25 26
1
2
3
4
5
6
7
8
9
52 51 50 49 48 47 46 45 44 43 42 41 40
39
38
37
36
35
34
33
32
31
30
29
28
27
10
11
12
13
Internal Voltage
Reference
2X
RGBOUT
DEMUX,
VREF FSADJUST
CVBS/G
Y/CVBS
C/R
DAC
DAC
DAC
Upsample
+
P[7:0]
8
NTSC
Blanking
Pedestal
SLAVE
Y
BLANK
Video
Timing
Control
RESET
Sync
Rise/Fall
Expander
+ +
1.3 MHz LPF
and 2X
Upsample
U/V
Modulator
10
CLK
SCL
SLEEP
SDA
and
Mixer
10 10
G
B
R
10
CVBS/B DAC
10
9
10
9
10
10
9
10
FIELD
HSYNC
VSYNC
COMP
BLANK
VBIAS
ALTADDR
Color
Space
Convert
Y[7:0]
8
I
2
C Interface
Captioning,
Macrovision
Closed
TTXREQ
TTXDAT
+
Luma
Delay
10
4:2:2 -> 4:4:4
Upsample,
Magnitude
Luminance
Teletext/
Scaling
CGMS
VDD3V
BT864A (IC401)
LDC O I/O
Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a control output
indicating that configuration is not yet completed. After configuration, LDC is a user-programmable I/O pin.
Before and during configuration, INIT is a bidirectional signal. A 1 k
Ω
to 10k
Ω
external pull-up resistor
is recommended.
As an active Low open-drain output, INIT is held Low during the power stabilization and internal
INIT I/O I/O
clearing of the configuration memory. As an active Low input, it can be used to hold the FPGA in the
internal WAIT state before the start of configuration. Master mode devices stay in a WAIT state an
additional 30 to 300
µ
s after INIT has gone High.
During configuration, a Low on this output indicates that a configuration data error has occurred. After
the I/O go active, INIT is a user-programmable I/O pin.
PGCK1-
Four Primary Global inputs each drive a dedicated internal global net with short delay and minimal
PGCK4
Weak
I or I/O
skew. If not used to drive a global buffer, any of these pins is a user-programmable I/O.
(Spartan)
Pull-up The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol connected
directly to the input of a BUFGP symbol is automatically placed on one of these pins.
Weak Four Secondary Global inputs each drive a dedicated internal global net with short delay and minimal
SGCK1- Pull-up skew. These internal global nets can also be driven from internal logic. If not used to drive a global net,
SGCK4 (except I or I/O any of these pins is a user-programmable I/O pin.
(Spartan) SGCK4 The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buffers. Any input pad
is DOUT) symbol connected directly to the input of a BUFGS symbol is automatically placed on one of these pins.
Weak Eight Global inputs each drive a dedicated internal global net with short delay and minimal skew. These
GCK1-GCK8
Pull-up internal global nets can also be driven from internal logic. If not used to drive a global net, any of these
(Spartan-XL)
(except I or I/O pins is a user-programmable I/O pin.
GCK6 is The GCK1-GCK8 pins provide the shortest path to the eight Global Low-Skew Buffers. Any input pad
DOUT) symbol connected directly to the input of a BUFGLS symbol is automatically placed on one of these pins.
CS1
I I/O During Express configuration, CS1 is used as a serial-enable signal for daisy-chaining.
(Spartan-XL)
D0-D7
I I/O
During Express configuration, these eight input pins receive configuration data.
(Spartan-XL) After configuration, they are user-programmable I/O pins.
DIN I I/O
During Slave Serial or Master Serial configuration, DIN is the serial configuration data input receiving
data on the rising edge of CCLK. After configuration, DIN is a user-programmable I/O pin.
During Slave Serial or Master Serial configuration, DOUT is the serial configuration data output that can
drive the DIN of daisy-chained slave FPGAs.
DOUT data changes on the falling edge of CCLK, one-and-a-half CCLK periods after it was received at
DOUT O I/O the DIN input.
In Spartan-XL Express mode, DOUT is the status output that can drive the CS1 of daisy-chained
FPGAs, to enable and disable downstream devices.
After configuration, DOUT is a user-programmable I/O pin.
Unrestricted User-Programmable I/O pins
Weak
These pins can be configured to be input and/or output after configuration is completed. Before
I/O
Pull-up
I/O configuration is completed, these pins have an internal high-value pull-up resistor network that defines
the logic level as High.