Denon DN-V1700, Service Manual

Page: 19 / 51

19
DN-V1700
LAN91C111-NC (IC216)
LAN91C111-NC Terminal Function
11 EEPROM Clock EESK O4 Output. 4
µ
sec clock used to shift data in and out of the serial EEPROM.
12 EEPROM Select EECS O4
Output. Serial EEPROM chip select. Used for selection and command framing
of the serial EEPROM.
9 EEPROM Data Out EEDO O4 Output. Connected to the DI input of the serial EEPROM.
10 EEPROM Data In EEDI
I with
Input. Connected to the DO output of the serial EEPROM.
pulldown**
5-7 I/O Base
IOS0- I with Input. External switches can be connected to these lines to select between
IOS2 pullup** predefined EEPROM configurations.
8
Enable
ENEEP
I with Input. Enables (when high or open) LAN91C111 accesses to the serial EEPROM.
EEPROM pullup** Must be grounded if no EEPROM is connected to the LAN91C111.
An external 25 MHz crystal is connected across these pins. If a TTL clock is
1,2
Crystal1 XTAL1
lclk**
supplied instead, it should be connected to XTAL1 and XTAL2 should be left
Crystal2 XTAL2 open. XTAL1 is the 5V tolerant input of the internal amplifier and XTAL2 is the
output of the internal amplifier.
3, 35, 46,
67, 79, 100,
Power VDD +3.3V Power supply pins.
112, 122
13, 18 Analog Power AVDD +3.3V Analog power supply pins.
26, 41, 54,
59, 69, 74, 95, Ground
GND Ground pins.
105, 110, 119
15,21 Analog Ground AGND Analog Ground pins.
23 Loopback LBK O4 Output. Active when LOOP bit is set (TCR bit1).
22 nLink Status nLNK
I with
Input. General-purpose input port used to convey LINK status (EPHSR bit 14).
pullup
30 nCNTRL nCNTRL O12 General Purpose Control Pin.
49 X25out X25out O12 25MHz Output to external PHY.
113
Transmit
TXEN100 O12 Output to MII PHY. Envelope to 100 Mbps transmission.
Enable 100 Mbps
121
Carrier Sense
CRS100
I with Input from MII PHY. Envelope of packet reception used for deferral and backoff
100 Mbps pulldown purposes.
1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
102 101 100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
XTAL1 XTAL2
VDD
nCSOUT
IOS0 IOS1 IOS2
ENEEP
EEDO
EEDI
EESK EECS AVDD
RBIAS
AGND
TPO+
TPO-
AVDD
TPI+
TPI-
AGND
nLNK
LBK
nLEDA nLEDB
GND
MDI
MDO
MCLK
nCNTRL
INTR0
RESET
nRD
nWR
VDD
nDATACS
nCYCLE
W/nR
D6 D7 VDD nBE3 nBE2 nBE1 nBE0 GND A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 VDD D8 D9 D10 D11 GND D12 D13 D14 D15 GND D16 D17 D18 D19
nADS
ARDY
GND
nVLBUS
AEN
LCLK
nSRDY
VDD
nLDEV
nRDYRTN
X25OUT
D31
D30
D29
D28
GND
D27
D26
D25
D24
GND
D23
D22
D21
D20
VDD
RX_ER
RX_DV
RXD0
RXD1
RXD2
RXD3
VDD
CRS100
RX25
GND
TXD0
TXD1
TXD2
TXD3
COL100
TXEN100
VDD
TX25
GND
D0
D1
D2
D3
GND
D4
D5
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
TOP VIEW
Description Pin No. Name
Buffer
Type
Symbol